From patchwork Wed Jun 7 21:27:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 9772873 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 60D456034B for ; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 711172843F for ; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 65CFF2847B; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07B2B28451 for ; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751428AbdFGV2M (ORCPT ); Wed, 7 Jun 2017 17:28:12 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62918 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751527AbdFGV2L (ORCPT ); Wed, 7 Jun 2017 17:28:11 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRXAU029833; Wed, 7 Jun 2017 16:27:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870853; bh=IqmstxIOnBTVQHj36jWgPcSrbwkKzwPPW8moivTOA9I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OE/E0gFyejzxBPPp3Ml2TVCp1rNd1N4oYbGt8O7mQxOes8UNsoNOYtBJVbxCYoUqF QWCMfb60Ou5PCqDHDnFd2AoyxJ0i8lnTZfmf2c/maILDMi0bTjoxJQNBXfgIA+JB1w xh5QvAJAtHDhxgSnxcfyS2akkRKcY0VoJ6tS1swU= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXQc004001; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:33 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXE2025580; Wed, 7 Jun 2017 16:27:33 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRX307118; Wed, 7 Jun 2017 16:27:33 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 5/6] ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:29 -0500 Message-ID: <20170607212730.33002-6-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD subsystem in DRA7xx as compared to previous OMAP generations when it provided the clocks for both DSP and IVAHD subsystems. This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset value of the divider M2 (that supplies the IVA_GFLCK, the functional clock for the IVAHD subsystem) does not match a specific OPP. So, the derived output clock from this IVA DPLL has to be initialized as well to avoid initializing these divider outputs to an incorrect frequencies. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so the dpll_iva_ck clock rate used is half of this value. The value for the divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more for the divider clk logic to compute the appropriate divider value for OPP_NOM. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8a82490035d9..76e2b7478141 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -376,6 +376,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { @@ -387,6 +389,8 @@ reg = <0x01b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m2_ck>; + assigned-clock-rates = <388333334>; }; iva_dclk: iva_dclk {