From patchwork Mon Aug 21 23:48:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 9913947 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 23EAD602D8 for ; Mon, 21 Aug 2017 23:48:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09624205AD for ; Mon, 21 Aug 2017 23:48:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F1A01252D5; Mon, 21 Aug 2017 23:48:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76106205AD for ; Mon, 21 Aug 2017 23:48:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753548AbdHUXst (ORCPT ); Mon, 21 Aug 2017 19:48:49 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45836 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753979AbdHUXss (ORCPT ); Mon, 21 Aug 2017 19:48:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmLPa028083; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=Fi5CiceZPtsesNcGp/0yXziImRc2GPvnyEOfM7qeK94=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=flJ1Rv02VMUXlF+zoSFH1bs1AN0jzNeU5dG0e4JtA1Zlcz08q0K46jGZtrW6+91WL Z1bh9IUsP700eqkQftK5dNTIOmdTq3NNiwxSg/MbU0BsY/pT7t2VdVDQMz9EgetIsy HGTDqiT6nQfhGvT+ONxT3u0mgs1ex0Su/1/MAaq8= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLlv002306; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLG3003481; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmK307092; Mon, 21 Aug 2017 18:48:20 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 4/8] ARM: OMAP2+: Extend iommu pdata-quirks to DRA7 DSPs Date: Mon, 21 Aug 2017 18:48:14 -0500 Message-ID: <20170821234818.4755-5-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DSP processor subsystem in DRA7xx SoCs has two MMUs, one for the processor port and another for an EDMA port. Both these MMUs share a common reset line, the MMU on the EDMA port will always be mirror-programmed alongside the primary MMU, with the reset handled once. The reset handling is the same as on equivalent DSP subsystems on OMAP4/OMAP5 SoCs, so extend the OMAP4 iommu pdata quirks for reset for the MMU associated with the processor port only. Add these pdata quirks for both the DSP1 and DSP2 processor subsystems. Note that DSP2 subsystem is present only on the DRA74x/DRA76x SoC variants and not on DRA72x/DRA71x SoCs. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/pdata-quirks.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 253315393a29..65e566f0c5ea 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -589,6 +589,10 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &dra7_hsmmc_data_mmc2), OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", + &omap4_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", + &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",