From patchwork Mon Aug 21 23:48:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 9913961 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F0F33608A6 for ; Mon, 21 Aug 2017 23:48:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE05F1FFB2 for ; Mon, 21 Aug 2017 23:48:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D2F95205AD; Mon, 21 Aug 2017 23:48:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B8AB723B24 for ; Mon, 21 Aug 2017 23:48:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753979AbdHUXsz (ORCPT ); Mon, 21 Aug 2017 19:48:55 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:14381 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754077AbdHUXsy (ORCPT ); Mon, 21 Aug 2017 19:48:54 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmMnU026870; Mon, 21 Aug 2017 18:48:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359302; bh=pu1IUM4oa/0Ygm0xhHlk+2UrlMrUW4j4oVIBAfAHorU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xChZD8kgVi5l+tx2V/lC5J2lAJSn5KBeRQkm6QRo6/KNagxUSyfJJMilJSV7tkEda eWoxGLLNlknCqC9+ZrlLxpIIsYFulHkZcTYRxXjOGF57+8PrBGCXAF7YlmXkUacAXL xsT2CNP5Ag3wmkMry7bemj39P7pvVwHuklsHBo8g= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmM4l002324; Mon, 21 Aug 2017 18:48:22 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLP9031307; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307105; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 7/8] ARM: DRA7: hwmod_data: Add data for IPUs Date: Mon, 21 Aug 2017 18:48:17 -0500 Message-ID: <20170821234818.4755-8-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DRA7xx family of SoCs usually have two IPU remote processor subsystems. These subsystems are very similar to the respective processor subsystems on OMAP4/OMAP5 in terms of clock and reset integration. The relevant hwmod classes and data structures are added for IPU1 and IPU2 remoteproc devices that's present on almost all DRA7xx/AM57xx SoCs. Do note that these hwmod data structures do not have a .modulemode field as the devices are managed together with their corresponding MMUs. Each of the processor subsystem and its MMU are present within the same clock domain and requires the domain be clocked and enabled until the last entity is disabled. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 66 +++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 63ad0d3217dc..e65a02855633 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1201,6 +1201,54 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { }; /* + * 'ipu' class + * image processor unit + */ + +static struct omap_hwmod_class dra7xx_ipu_hwmod_class = { + .name = "ipu", +}; + +static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, + { .name = "cpu1", .rst_shift = 1 }, +}; + +/* ipu1 processor */ +static struct omap_hwmod dra7xx_ipu1_hwmod = { + .name = "ipu1", + .class = &dra7xx_ipu_hwmod_class, + .clkdm_name = "ipu1_clkdm", + .rst_lines = dra7xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets), + .main_clk = "ipu1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET, + }, + }, +}; + +/* ipu2 processor */ +static struct omap_hwmod dra7xx_ipu2_hwmod = { + .name = "ipu2", + .class = &dra7xx_ipu_hwmod_class, + .clkdm_name = "ipu2_clkdm", + .rst_lines = dra7xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mailbox' class * */ @@ -3492,6 +3540,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* ipu1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = { + .master = &dra7xx_ipu1_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = { + .master = &dra7xx_ipu2_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> mailbox1 */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { .master = &dra7xx_l4_cfg_hwmod, @@ -4171,6 +4235,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_ipu1__l3_main_1, + &dra7xx_ipu2__l3_main_1, &dra7xx_l4_cfg__mailbox1, &dra7xx_l4_per3__mailbox2, &dra7xx_l4_per3__mailbox3,