From patchwork Fri Sep 29 16:44:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 9978421 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B80A960311 for ; Fri, 29 Sep 2017 16:45:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA97B2988B for ; Fri, 29 Sep 2017 16:45:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9EA452988C; Fri, 29 Sep 2017 16:45:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EE4229538 for ; Fri, 29 Sep 2017 16:45:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752214AbdI2Qog (ORCPT ); Fri, 29 Sep 2017 12:44:36 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:64682 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752159AbdI2Qod (ORCPT ); Fri, 29 Sep 2017 12:44:33 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8TGiUBg024863; Fri, 29 Sep 2017 11:44:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506703470; bh=SLMqUSEaDaRDWIlPxceg63oTvzsoEkUeuqJ4AkZtpEk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UUVhNnQ2a6HBV4QOhUl3EXmHJUCs4PRzecgK1Xe6kpBW5oOakrhy3fqDj3/zRy1kl TWlcEiEzVhyhLu2Yvt4ux9yqxc+GCpTIRRubgK5a+0CxcM1RqZ6g5ExTmj8QuHnA8t JDmfWaF3aHwIHYxKS1/02Gm17lCekzNqAmR/kGq0= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8TGiUEY024289; Fri, 29 Sep 2017 11:44:30 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 29 Sep 2017 11:44:30 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 29 Sep 2017 11:44:30 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8TGiUfE007567; Fri, 29 Sep 2017 11:44:30 -0500 Received: from localhost (uda0226330.dhcp.ti.com [128.247.58.138]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v8TGiT309409; Fri, 29 Sep 2017 11:44:29 -0500 (CDT) From: "Andrew F. Davis" To: =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren CC: , , "Andrew F . Davis" Subject: [PATCH 01/11] ARM: dts: am43xx: Introduce additional pinmux definitions for DS0 Date: Fri, 29 Sep 2017 11:44:19 -0500 Message-ID: <20170929164429.780-2-afd@ti.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170929164429.780-1-afd@ti.com> References: <20170929164429.780-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP AM43xx platform pinmux registers contain bits to set state during suspend (DS0), add these bit definitions here. Signed-off-by: Andrew F. Davis --- include/dt-bindings/pinctrl/am43xx.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index 344bd1eb3386..fc31ef7ce219 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -21,9 +21,21 @@ #define INPUT_EN (1 << 18) #define SLEWCTRL_SLOW (1 << 19) #define SLEWCTRL_FAST 0 +#define DS0_FORCE_OFF_MODE (1 << 24) +#define DS0_INPUT (1 << 25) +#define DS0_FORCE_OUT_HIGH (1 << 26) #define DS0_PULL_UP_DOWN_EN (1 << 27) +#define DS0_PULL_UP_SEL (1 << 28) #define WAKEUP_ENABLE (1 << 29) +#define DS0_PIN_OUTPUT (DS0_FORCE_OFF_MODE) +#define DS0_PIN_OUTPUT_HIGH (DS0_FORCE_OFF_MODE | DS0_FORCE_OUT_HIGH) +#define DS0_PIN_OUTPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) +#define DS0_PIN_OUTPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN) +#define DS0_PIN_INPUT (DS0_FORCE_OFF_MODE | DS0_INPUT) +#define DS0_PIN_INPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) +#define DS0_PIN_INPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN) + #define PIN_OUTPUT (PULL_DISABLE) #define PIN_OUTPUT_PULLUP (PULL_UP) #define PIN_OUTPUT_PULLDOWN 0