diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 5bdca62fdd54..10e80bdde5ee 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -25,11 +25,6 @@
 
 #define	ONENAND_IO_SIZE	SZ_128K
 
-#define	ONENAND_FLAG_SYNCREAD	(1 << 0)
-#define	ONENAND_FLAG_SYNCWRITE	(1 << 1)
-
-static unsigned onenand_flags;
-
 static struct omap_onenand_platform_data *gpmc_onenand_data;
 
 static struct resource gpmc_onenand_resource = {
@@ -83,7 +78,8 @@ static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
 	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
-static void set_onenand_cfg(void __iomem *onenand_base, int latency)
+static void set_onenand_cfg(void __iomem *onenand_base,
+			    bool sr, bool sw, int latency)
 {
 	u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
 
@@ -93,14 +89,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency)
 		reg |= ONENAND_SYS_CFG1_HF;
 	if (latency > 7)
 		reg |= ONENAND_SYS_CFG1_VHF;
-	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
+	if (sr)
 		reg |= ONENAND_SYS_CFG1_SYNC_READ;
-	else
-		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
+	if (sw)
 		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
-	else
-		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
 
 	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
@@ -148,6 +140,9 @@ static int omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
 	int div, gpmc_clk_ns, latency;
 
+	if (!s->sync_read && !s->sync_write)
+		return 0;
+
 	switch (freq) {
 	case 104:
 		min_gpmc_clk_period = 9600; /* 104 MHz */
@@ -184,7 +179,8 @@ static int omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
 		t_ach   = 9;
 		t_aavdh = 7;
 		t_rdyo  = 15;
-		onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
+		s->sync_write = false;
+		s->burst_write = false;
 		break;
 	}
 
@@ -202,12 +198,7 @@ static int omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
 	/* Set synchronous read timings */
 	memset(&dev_t, 0, sizeof(dev_t));
 
-	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
-		s->sync_read = true;
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-		s->sync_write = true;
-		s->burst_write = true;
-	} else {
+	if (!s->sync_write) {
 		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
 		dev_t.t_wpl = t_wpl * 1000;
 		dev_t.t_wph = t_wph * 1000;
@@ -246,14 +237,9 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
 	 * supported clock rate for the sync timings.
 	 */
 	gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s);
-	if (s.sync_read || s.sync_write) {
-		onenand_flags |= ONENAND_FLAG_SYNCREAD;
-		if (s.sync_write)
-			onenand_flags |= ONENAND_FLAG_SYNCWRITE;
-		s.sync_read = false;
-	}
-
+	s.sync_read = false;
 	s.sync_write = true;
+
 	omap2_onenand_calc_async_timings(&t, &s);
 
 	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s);
@@ -285,16 +271,18 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
 	gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s);
 
 	latency = omap2_onenand_calc_sync_timings(&t, &s, freq);
+	if (latency > 0) {
+		ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s);
+		if (ret < 0)
+			return ret;
 
-	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s);
-	if (ret < 0)
-		return ret;
+		ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s);
+		if (ret < 0)
+			return ret;
 
-	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s);
-	if (ret < 0)
-		return ret;
-
-	set_onenand_cfg(onenand_base, latency);
+		set_onenand_cfg(onenand_base, s.sync_read, s.sync_write,
+				latency);
+	}
 
 	*freq_ptr = freq;
 
@@ -304,7 +292,6 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
 	struct device *dev = &gpmc_onenand_device.dev;
-	unsigned l = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 	int ret;
 
 	ret = omap2_onenand_setup_async(onenand_base);
@@ -313,9 +300,6 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 		return ret;
 	}
 
-	if (!(onenand_flags & l))
-		return 0;
-
 	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
 	if (ret)
 		dev_err(dev, "unable to set to sync mode\n");
