From patchwork Tue Nov 14 22:46:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 10058511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 007586023A for ; Tue, 14 Nov 2017 22:46:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E63372997C for ; Tue, 14 Nov 2017 22:46:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA43929994; Tue, 14 Nov 2017 22:46:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C7162997C for ; Tue, 14 Nov 2017 22:46:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757232AbdKNWqo (ORCPT ); Tue, 14 Nov 2017 17:46:44 -0500 Received: from eddie.linux-mips.org ([148.251.95.138]:37310 "EHLO cvs.linux-mips.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757122AbdKNWqe (ORCPT ); Tue, 14 Nov 2017 17:46:34 -0500 Received: (from localhost user: 'ladis' uid#1021 fake: STDIN (ladis@eddie.linux-mips.org)) by eddie.linux-mips.org id S23990765AbdKNWqapl8c1 (ORCPT ); Tue, 14 Nov 2017 23:46:30 +0100 Date: Tue, 14 Nov 2017 23:46:29 +0100 From: Ladislav Michl To: Tony Lindgren Cc: linux-mtd@lists.infradead.org, linux-omap@vger.kernel.org, Roger Quadros , Peter Ujfalusi , Boris Brezillon , Kyungmin Park , Aaro Koskinen Subject: Re: [PATCH v4 16/16] ARM: dts: Nokia: Use R/B pin Message-ID: <20171114224629.ybnpoleepgdzbqka@lenoch> References: <20171111211206.465pgorrjp3eyix6@lenoch> <20171111212939.jcf26v3w26bd7sn7@lenoch> <20171114214256.GG28152@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20171114214256.GG28152@atomide.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, Nov 14, 2017 at 01:42:56PM -0800, Tony Lindgren wrote: > * Ladislav Michl [171111 21:31]: > > Enable use of R/B pin. This is just experimental placeholder patch > > as it lacks pinmux settings. > > > > Signed-off-by: Ladislav Michl > > --- > > Changes: > > -v4: new patch > > > > arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 4 +--- > > arch/arm/boot/dts/omap3-n900.dts | 1 + > > 2 files changed, 2 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi > > index 843f6a2f5e29..cfe5d02ea0ed 100644 > > --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi > > +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi > > @@ -42,14 +42,12 @@ > > > > &gpmc { > > ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ > > - > > - /* gpio-irq for dma: 26 */ > > - > > onenand@0,0 { > > #address-cells = <1>; > > #size-cells = <1>; > > compatible = "ti,omap2-onenand"; > > reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ > > + rb-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; > > > > gpmc,sync-read; > > gpmc,burst-length = <16>; > > > This should be then <&gpio1 26 GPIO_ACTIVE_HIGH>, there is no &gpio0. This > will produce a build error too. Argh, you're right. Fixed bellow. > > diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts > > index aa5b1a439564..718116d9f4ac 100644 > > --- a/arch/arm/boot/dts/omap3-n900.dts > > +++ b/arch/arm/boot/dts/omap3-n900.dts > > @@ -840,6 +840,7 @@ > > #size-cells = <1>; > > compatible = "ti,omap2-onenand"; > > reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ > > + rb-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; > > > > gpmc,sync-read; > > gpmc,sync-write; > > This worked for me on n900, I'm currently unable to test n8x0. > But might be worth double checking if &gpio3 is correct here? I hope so. This is what original platform data used and what was in omap3-n900.dts comment prior to e2c5eb78a3cc. Also see i2c0 node in omap2420-n8x0-common.dtsi. Here's quick update, v5 will follow after receiving some more testing. And of course thanks a lot for testing! --- arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 4 +--- arch/arm/boot/dts/omap3-n900.dts | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 843f6a2f5e29..80cbbe0ee844 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -42,14 +42,12 @@ &gpmc { ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - /* gpio-irq for dma: 26 */ - onenand@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + rb-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; /* gpio_26 for R/B */ gpmc,sync-read; gpmc,burst-length = <16>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index aa5b1a439564..669899fd080b 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -834,12 +834,12 @@ pinctrl-names = "default"; pinctrl-0 = <&gpmc_pins>; - /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + rb-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; /* gpio_65 for R/B */ gpmc,sync-read; gpmc,sync-write;