From patchwork Tue Dec 19 08:58:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 10122775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AED06603B5 for ; Tue, 19 Dec 2017 09:03:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A09BA285F9 for ; Tue, 19 Dec 2017 09:03:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9521C286F4; Tue, 19 Dec 2017 09:03:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5307C28685 for ; Tue, 19 Dec 2017 09:03:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966706AbdLSI6s (ORCPT ); Tue, 19 Dec 2017 03:58:48 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:15888 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933786AbdLSI6o (ORCPT ); Tue, 19 Dec 2017 03:58:44 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ8wdQZ019722; Tue, 19 Dec 2017 02:58:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513673919; bh=5Qy5dcr/i7WhyEWJNjUKajSJEJsaDJU8FMOL2iy8O/c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xkgSvAEsRrZgM4IojHrJUHrtvEX91hJzIsCB598amVROSxyuMgMUs7j1XvVSvqNGH Oxo357uQA0uOMd201EhzF87nCNnR1CVZY+Zy7JBqomt+3sT4y4h36S9HCA93P1QEtx fiOKie+RCcbes1Zf8C3CtWuSzNfVTZNPYoCrsT7M= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ8wdsk015199; Tue, 19 Dec 2017 02:58:39 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 02:58:39 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 02:58:39 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ8wTaq021479; Tue, 19 Dec 2017 02:58:36 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring CC: Mark Rutland , , , , , , Subject: [PATCH v2 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Date: Tue, 19 Dec 2017 14:28:22 +0530 Message-ID: <20171219085823.8695-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219085823.8695-1-kishon@ti.com> References: <20171219085823.8695-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 82cb875e4cec..bfbc77ac7355 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,12 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system control + module and the register offset to specify 1 lane or + 2 lane. + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control + module and the register offset to specify lane + selection. HOST MODE =========