From patchwork Tue Feb 6 12:58:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 10202955 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6FEBE605BA for ; Tue, 6 Feb 2018 13:00:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 553B12883B for ; Tue, 6 Feb 2018 13:00:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 495FD288C5; Tue, 6 Feb 2018 13:00:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D3EB228898 for ; Tue, 6 Feb 2018 13:00:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752839AbeBFNAB (ORCPT ); Tue, 6 Feb 2018 08:00:01 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:15749 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753133AbeBFM7g (ORCPT ); Tue, 6 Feb 2018 07:59:36 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w16Cx4AB013014; Tue, 6 Feb 2018 06:59:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517921944; bh=o0g9u0uPxz92YWAz45A+6p1Ey4LMEOnmdzYZ2E+8DDY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nufg6padsn0uvmyU3++pqXSwnDkYpF090rKtAAZOwTuyZGrqIGwyVqPvUPlGbnRBo LJ2XqUYdKplsu4F0Vc6Dvhpj8wjtM3dgxiLlOygJj7nKaTowZyRXd7e+g6vlIODgPh mRU+G1M0ZuhLNBQXnau5jz0EN8EM3HgAu7k1KGFs= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16Cx4Um006780; Tue, 6 Feb 2018 06:59:04 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 6 Feb 2018 06:59:03 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 6 Feb 2018 06:59:03 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwHXh007055; Tue, 6 Feb 2018 06:59:01 -0600 From: Kishon Vijay Abraham I To: =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Kishon Vijay Abraham I Subject: [PATCH v2 13/15] ARM: dts: am57xx-idk: Select pull down for mmc1_clk line in default mode Date: Tue, 6 Feb 2018 18:28:04 +0530 Message-ID: <20180206125806.19350-14-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP During a short period when the bus voltage is switched from 3.3v to 1.8v, (to enumerate UHS mode), the mmc module is disabled and the mmc IO lines are kept in a state according to the programmed pad mux pull type. According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the host should hold CLK low for at least 5ms. In order to keep the card line low during voltage switch, the pad mux of mmc1_clk line should be configured to pull down. This is specific to am57xx-idk (and not all dra72/dra74 based boards) since mmc1_clk line in am57xx-idk is not connected to an external pullup. While at that change the order of header files in am571x-idk.dts and am572x-idk.dts so that the modified pinctrl values in am57xx-idk-common could take effect. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am571x-idk.dts | 2 +- arch/arm/boot/dts/am572x-idk.dts | 3 +-- arch/arm/boot/dts/am57xx-idk-common.dtsi | 11 +++++++++++ 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 6d3c83743156..a2555140babc 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -10,8 +10,8 @@ #include "dra72x.dtsi" #include #include -#include "am57xx-idk-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" +#include "am57xx-idk-common.dtsi" / { model = "TI AM5718 IDK"; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 9ab0af5017df..3a02ed720957 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -9,9 +9,8 @@ /dts-v1/; #include "dra74x.dtsi" -#include "am572x-idk-common.dtsi" -#include "am57xx-idk-common.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "am572x-idk-common.dtsi" / { model = "TI AM5728 IDK"; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 43a6d0590f7c..43cdf523a8a0 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -115,6 +115,17 @@ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ >; }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; }; &i2c1 {