From patchwork Thu Apr 26 11:51:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10365721 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8CFD26054A for ; Thu, 26 Apr 2018 11:51:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F12A27F60 for ; Thu, 26 Apr 2018 11:51:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 73B7027F9F; Thu, 26 Apr 2018 11:51:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1847827F60 for ; Thu, 26 Apr 2018 11:51:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755385AbeDZLvY (ORCPT ); Thu, 26 Apr 2018 07:51:24 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:9053 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755413AbeDZLvV (ORCPT ); Thu, 26 Apr 2018 07:51:21 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3QBopPg026504; Thu, 26 Apr 2018 06:50:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524743451; bh=yVmkG9HwOSnMYG/8WIWBwIi2hjm7b2ZA/XRDB88fS0o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Icg/iBYEyCUE4DR6abw9feyYQnk2cvkWggsWfvXGV2BZXSfK0A48x03B6odHGc3gv 3nBNE1hoPIMPpdnEx+VFoJUnL3SdLUBQfy1RfrYKlGLt3qTGzpSZeITAsH5nHHhiS6 WdTv4BOn6ZeeZ9LJLR4CpFncfc4HseSMFOz8FwUM= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3QBopYc008386; Thu, 26 Apr 2018 06:50:51 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 26 Apr 2018 06:50:50 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 26 Apr 2018 06:50:50 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3QBoick024090; Thu, 26 Apr 2018 06:50:49 -0500 From: Peter Ujfalusi To: Mark Brown , Liam Girdwood , , CC: , , Subject: [PATCH 2/5] ARM: dts: omap2420-n810: Correct the audio codec (tlv320aic33) node Date: Thu, 26 Apr 2018 14:51:12 +0300 Message-ID: <20180426115115.13744-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180426115115.13744-1-peter.ujfalusi@ti.com> References: <20180426115115.13744-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The n810 uses tlv320aic33 codec. GPIO118 is used as reset GPIO for the codec, which was missing. The MCLK of the codec is connected to the SYS_CLKOUT2 of omap2420. The SYS_CLKOUT2 needs to be running at 12MHz. Add the pinctrl entries to configure the pins for GPIO118 and SYS_CLKOUT2. Signed-off-by: Peter Ujfalusi Tested-by: Jarkko Nikula --- arch/arm/boot/dts/omap2420-n810.dts | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts index 4c412a480c3e..db4c8a7a1a84 100644 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ b/arch/arm/boot/dts/omap2420-n810.dts @@ -17,14 +17,31 @@ OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ >; }; + + aic33_pins: aic33_pins { + pinctrl-single,pins = < + OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ + OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ + >; + }; }; &i2c2 { - aic3x@18 { - compatible = "tlv320aic3x"; + aic33@18 { + compatible = "ti,tlv320aic33"; reg = <0x18>; + + pinctrl-names = "default"; + pinctrl-0 = <&aic33_pins>; + + gpio-reset = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ + + assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>; + assigned-clock-parents = <&func_96m_ck>; + assigned-clock-rates = <0>, <12000000>; }; }; + &mcbsp2 { pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>;