From patchwork Fri Apr 27 12:09:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 10368365 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 01D9D601D3 for ; Fri, 27 Apr 2018 12:10:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E5707293C6 for ; Fri, 27 Apr 2018 12:10:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D852B29402; Fri, 27 Apr 2018 12:10:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 29156293D6 for ; Fri, 27 Apr 2018 12:10:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932372AbeD0MKJ (ORCPT ); Fri, 27 Apr 2018 08:10:09 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:49490 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758191AbeD0MKF (ORCPT ); Fri, 27 Apr 2018 08:10:05 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RC9xKW029254; Fri, 27 Apr 2018 07:09:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524830999; bh=i7EtzaHi8CqTnLSqHHFojJiAr1Ljb4E40Vbib6cP/jI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zQZprF2LGgzBdNoTL0nIaTuZseol+cjJyUGrR5E6YPjVq1taR53Hiz/lkOQxczl5q +hW50MZUSqj1UoHRZ9FZ5D9TeWU+0syi1kOn3kWravQoKoxTmkU4uybiXPL4v2xBd+ DI9rPn0LOJw9kQuAgsatrtqBLmhtqVUXEG42QjkI= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9xlF013140; Fri, 27 Apr 2018 07:09:59 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 07:09:58 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 07:09:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9AjV006789; Fri, 27 Apr 2018 07:09:56 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren CC: Jonathan Corbet , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Rob Herring , Mark Rutland , , , , , Subject: [PATCH v4 13/14] ARM: dts: dra7: Add high speed modes capability to MMC1/MMC2 dt node Date: Fri, 27 Apr 2018 17:39:04 +0530 Message-ID: <20180427120905.3665-14-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427120905.3665-1-kishon@ti.com> References: <20180427120905.3665-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP While the supported UHS mode can be obtained from CAPA2 register, SD Host Controller Standard Specification doesn't define bits for MMC's HS200 and DDR mode capability. Add properties to indicate MMC HS200 and DDR speed mode capability in dt node. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ae2f8dd46328..9dcd14edc202 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1086,6 +1086,8 @@ status = "disabled"; pbias-supply = <&pbias_mmc_reg>; max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; }; hdqw1w: 1w@480b2000 { @@ -1104,6 +1106,9 @@ max-frequency = <192000000>; /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ sdhci-caps-mask = <0x7 0x0>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + mmc-ddr-3_3v; }; mmc3: mmc@480ad000 {