From patchwork Wed Jun 27 12:29:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10491903 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0CA0B601A0 for ; Wed, 27 Jun 2018 14:59:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3732E293FF for ; Wed, 27 Jun 2018 14:59:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BA1E29421; Wed, 27 Jun 2018 14:59:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C64E7293FF for ; Wed, 27 Jun 2018 14:59:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965318AbeF0O7R (ORCPT ); Wed, 27 Jun 2018 10:59:17 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43516 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752927AbeF0O7P (ORCPT ); Wed, 27 Jun 2018 10:59:15 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5RCSnDs056223; Wed, 27 Jun 2018 07:28:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1530102529; bh=r4QmPBPfwvBfvwSOY7PvLeKWRHtXCotnnhf+u63NpB8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vXWK2sEs5Qtp3U8XBnOVYD6sJNythNn6TFUqkMlABl0Ze/cvN9nnamjKhZ7u3tl0x Onvv7WOXRAYsDfbJLXY4vjZywsHJNhj2wPXDISe8cFUQSD+uEx05oJUM9hrA3OnwyA Qt3R2N3PLU6sBHTJPzW0LMTtnsWtsIvsuY4XHYgw= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5RCSnlr000698; Wed, 27 Jun 2018 07:28:49 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 27 Jun 2018 07:28:49 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 27 Jun 2018 07:28:49 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5RCSgMs027559; Wed, 27 Jun 2018 07:28:46 -0500 From: Vignesh R To: Tony Lindgren , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi CC: Bjorn Helgaas , , , , , Vignesh R Subject: [PATCH v2 1/4] dt-bindings: PCI: dra7xx: Add bindings for unaligned access in host mode Date: Wed, 27 Jun 2018 17:59:16 +0530 Message-ID: <20180627122919.23926-2-vigneshr@ti.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180627122919.23926-1-vigneshr@ti.com> References: <20180627122919.23926-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update device tree binding documentation of TI's dra7xx PCI controller for enabling unaligned mem access as applicable not just in EP mode but in host mode as well. Signed-off-by: Vignesh R Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 7f7af3044016..452fe48c4fdd 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -26,6 +26,11 @@ HOST MODE ranges, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. DEVICE MODE ===========