From patchwork Wed Jun 27 12:29:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10491911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D3F4060230 for ; Wed, 27 Jun 2018 14:59:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A6D4293FF for ; Wed, 27 Jun 2018 14:59:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2C9229421; Wed, 27 Jun 2018 14:59:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A39E5293FF for ; Wed, 27 Jun 2018 14:59:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964908AbeF0O7n (ORCPT ); Wed, 27 Jun 2018 10:59:43 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43516 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753490AbeF0O7O (ORCPT ); Wed, 27 Jun 2018 10:59:14 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5RCSunb056401; Wed, 27 Jun 2018 07:28:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1530102536; bh=SSIqg5g1fcJtfXsuuvcJWcucudI5cFsl5zYdO3mEPgI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V7k9CX+XFRM9Gc1OtL5KJwUHa8+jUaO3rZ7mU6RQoddDMNxrKhXkTgBxYvGDr/ipp 1G8PVIlhrOUCpyN2Ndg14kqwRGD6tJNP1za+imMBY+rp9NfoYgwe6Oj8YQsaEdoHUa fkVlCUP5/nFGqF3F8GUQU3Yi0hsEPbaIdbz4caBs= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5RCSuaG000783; Wed, 27 Jun 2018 07:28:56 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 27 Jun 2018 07:28:55 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 27 Jun 2018 07:28:55 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5RCSgMu027559; Wed, 27 Jun 2018 07:28:53 -0500 From: Vignesh R To: Tony Lindgren , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi CC: Bjorn Helgaas , , , , , Vignesh R Subject: [PATCH v2 3/4] ARM: dts: dra7: Enable workaround for errata i870 in PCIe host mode Date: Wed, 27 Jun 2018 17:59:18 +0530 Message-ID: <20180627122919.23926-4-vigneshr@ti.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180627122919.23926-1-vigneshr@ti.com> References: <20180627122919.23926-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add ti,syscon-unaligned-access property to PCIe RC nodes to set appropriate bits in CTRL_CORE_SMA_SW_7 register to enable workaround for errata i870. Signed-off-by: Vignesh R --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 93fc2d79d337..7bfe7f28e3bd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -336,6 +336,7 @@ <0 0 0 2 &pcie1_intc 2>, <0 0 0 3 &pcie1_intc 3>, <0 0 0 4 &pcie1_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; @@ -387,6 +388,7 @@ <0 0 0 2 &pcie2_intc 2>, <0 0 0 3 &pcie2_intc 3>, <0 0 0 4 &pcie2_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; pcie2_intc: interrupt-controller { interrupt-controller; #address-cells = <0>;