From patchwork Mon Sep 17 18:06:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10603267 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 754C4161F for ; Mon, 17 Sep 2018 18:06:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C3DC29095 for ; Mon, 17 Sep 2018 18:06:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4E3362A2F2; Mon, 17 Sep 2018 18:06:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0095A29095 for ; Mon, 17 Sep 2018 18:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728293AbeIQXeb (ORCPT ); Mon, 17 Sep 2018 19:34:31 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52908 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727052AbeIQXea (ORCPT ); Mon, 17 Sep 2018 19:34:30 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8HI5qVD088051; Mon, 17 Sep 2018 13:05:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537207552; bh=G34/AhswT8fOY3yqk7Zc580LLfv4PvRh4GF91gMUaWI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IotkgfP/JJnZMNt+Htog/BLzVwa9oKvVmudMS5gL+CwLQgt7L8MVcw6jLbYQUu786 meKaATRD+RBm0AfIcgqZ8j3n4cEZidcYLXALnUH2+Ps64EGQyVP0+mt5wsJ1Xo6CgF W9ocgmvNv9SIaHTMIkaN74xio5z/b5ukJFES7I30= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8HI5qME013217; Mon, 17 Sep 2018 13:05:52 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 17 Sep 2018 13:05:52 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 17 Sep 2018 13:05:52 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8HI5k1C004762; Mon, 17 Sep 2018 13:05:49 -0500 From: Vignesh R To: Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , , , , , Vignesh R Subject: [PATCH v4 1/2] dt-bindings: PCI: dra7xx: Add bindings for unaligned access in host mode Date: Mon, 17 Sep 2018 23:36:34 +0530 Message-ID: <20180917180635.26996-2-vigneshr@ti.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180917180635.26996-1-vigneshr@ti.com> References: <20180917180635.26996-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update device tree binding documentation of TI's dra7xx PCI controller for enabling unaligned mem access as applicable not just in EP mode but in host mode as well. Signed-off-by: Vignesh R Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 7f7af3044016..452fe48c4fdd 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -26,6 +26,11 @@ HOST MODE ranges, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. DEVICE MODE ===========