From patchwork Tue Sep 25 05:21:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10613351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9911915A6 for ; Tue, 25 Sep 2018 05:21:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BAAA298B4 for ; Tue, 25 Sep 2018 05:21:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7FC0829903; Tue, 25 Sep 2018 05:21:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07523298B4 for ; Tue, 25 Sep 2018 05:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725987AbeIYL04 (ORCPT ); Tue, 25 Sep 2018 07:26:56 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:55568 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725959AbeIYL04 (ORCPT ); Tue, 25 Sep 2018 07:26:56 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8P5L6ca055826; Tue, 25 Sep 2018 00:21:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537852866; bh=fjF9HZbvcu0Z1MzF3QlSMLBF+Rnjc3iSIAtXSFFGTBU=; h=From:To:CC:Subject:Date; b=Kjs+UAA79abeewkHNnh9/XZH88upY+x5KejAJRC4sdAX3IRYcPJYhsaQo9zgkMXiD 6ni1nNNpN5ZdpjWqEA+zSHAzNgb7SunKq2Im5+JJdZmMH3KGshrgNGRE5TQ0nJ+Rsm hoYT62JLbMUFXoOpm01p6SFrijFKbG+IHf5ldG4Y= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8P5L61N013956; Tue, 25 Sep 2018 00:21:06 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 25 Sep 2018 00:21:06 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 25 Sep 2018 00:21:06 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8P5L2iI020310; Tue, 25 Sep 2018 00:21:04 -0500 From: Vignesh R To: Tony Lindgren CC: , , , Vignesh R Subject: [PATCH v4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP Date: Tue, 25 Sep 2018 10:51:51 +0530 Message-ID: <20180925052151.9537-1-vigneshr@ti.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are incorrectly documented in the TRM. In fact, the bit positions are swapped. Update the DT bindings for PCIe EP to reflect the same. Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode") Cc: stable@vger.kernel.org Signed-off-by: Vignesh R --- This patch is split from v3 here: https://lore.kernel.org/patchwork/cover/967020/ Patch can be applied standalone and has no dependencies on other patches in v3. arch/arm/boot/dts/dra7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1050da6c6d35..fc50d6a8e51a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -355,7 +355,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; - ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; }; };