[20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms

Message ID	20190114132424.6445-21-kishon@ti.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-omap-owner@kernel.org> From: Kishon Vijay Abraham I <kishon@ti.com> To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Rob Herring <robh+dt@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Kishon Vijay Abraham I <kishon@ti.com>, Jingoo Han <jingoohan1@gmail.com>, Bjorn Helgaas <bhelgaas@google.com>, Mark Rutland <mark.rutland@arm.com>, Arnd Bergmann <arnd@arndb.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Murali Karicheri <m-karicheri2@ti.com>, Jesper Nilsson <jesper.nilsson@axis.com>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-arm-kernel@axis.com> Subject: [PATCH 20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms Date: Mon, 14 Jan 2019 18:54:20 +0530 Message-ID: <20190114132424.6445-21-kishon@ti.com> In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-omap-owner@vger.kernel.org Precedence: bulk
Series	Add support for PCIe RC and EP mode in TI's AM654 SoC \| expand [00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC [01/24] PCI: keystone: Add start_link/stop_link dw_pcie_ops [02/24] PCI: keystone: Cleanup error_irq configuration [03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information [04/24] PCI: keystone: Perform host initialization in a single function [05/24] PCI: keystone: Use platform_get_resource_byname to get memory resources [06/24] PCI: keystone: Move initializations to appropriate places [07/24] dt-bindings: PCI: Add dt-binding to configure PCIe mode [08/24] PCI: keystone: Explicitly set the PCIe mode [09/24] dt-bindings: PCI: Document "atu" reg-names [10/24] PCI: dwc: Enable iATU unroll for endpoint too [11/24] PCI: dwc: Fix ATU identification for designware version >= 4.80 [12/24] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 [13/24] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 [14/24] PCI: keystone: Add support for PCIe RC in AM654x Platforms [15/24] PCI: keystone: Invoke phy_reset API before enabling PHY [16/24] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs [17/24] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops [18/24] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset [19/24] PCI: dwc: Add callbacks for accessing dbi2 address space [20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms [21/24] PCI: designware-ep: Configure RESBAR to advertise the smallest size [22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts [23/24] misc: pci_endpoint_test: Add support to test PCI EP in AM654x [24/24] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test

diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 0bb19e268a8a..ae3465fd194b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -105,14 +105,33 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW_HOST help Say Y here if you want to enable PCI controller support on Keystone SoCs. The PCI controller on Keystone is based on DesignWare hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. +if PCI_KEYSTONE + +config PCI_KEYSTONE_HOST + bool "PCI Keystone Host Mode" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + default y + help + Enables support for the PCIe controller in the Keystone SoC to work in + host mode. + +config PCI_KEYSTONE_EP + bool "PCI Keystone Endpoint Mode" + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables support for the PCIe controller in the Keystone SoC to work in + endpoint mode. + +endif + config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e2f4e7c01b5a..adeb3565c11d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -50,6 +50,12 @@ #define OB_ENABLEN BIT(0) #define OB_WIN_SIZE 8 /* 8MB */ +#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) +#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) +#define PCIE_EP_IRQ_SET 0x64 +#define PCIE_EP_IRQ_CLR 0x68 +#define INT_ENABLE BIT(0) + /* IRQ register defines */ #define IRQ_EOI 0x050 @@ -90,11 +96,16 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 +#define AM654_WIN_SIZE SZ_64K + +#define APP_ADDR_SPACE_0 (16 * SZ_1K) #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct ks_pcie_of_data { + enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; unsigned int version; }; @@ -850,12 +861,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } +static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u32 val; + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_read(base + reg, size, &val); + ks_pcie_clear_dbi_mode(ks_pcie); + return val; +} + +static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_write(base + reg, size, val); + ks_pcie_clear_dbi_mode(ks_pcie); +} + static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, + .read_dbi2 = ks_pcie_am654_read_dbi2, + .write_dbi2 = ks_pcie_am654_write_dbi2, }; +static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + int flags; + + ep->page_size = AM654_WIN_SIZE; + flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); +} + +static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + u8 int_pin; + + int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); + if (int_pin == 0 || int_pin > 4) + return; + + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), + INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); + mdelay(1); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), + INT_ENABLE); +} + +static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + ks_pcie_am654_raise_legacy_irq(ks_pcie); + break; + case PCI_EPC_IRQ_MSI: + dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + break; + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features ks_pcie_am654_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = true, + .reserved_bar = 1 << BAR_0 | 1 << BAR_1, + .bar_fixed_64bit = 1 << BAR_0, + .bar_fixed_size[2] = SZ_1M, + .bar_fixed_size[3] = SZ_64K, + .bar_fixed_size[4] = 256, + .bar_fixed_size[5] = SZ_1M, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +ks_pcie_am654_get_features(struct dw_pcie_ep *ep) +{ + return &ks_pcie_am654_epc_features; +} + +static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { + .ep_init = ks_pcie_am654_ep_init, + .raise_irq = ks_pcie_am654_raise_irq, + .get_features = &ks_pcie_am654_get_features, +}; + +static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = ks_pcie->pci; + + ep = &pci->ep; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + return 0; +} + static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { int num_lanes = ks_pcie->num_lanes; @@ -923,7 +1061,8 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } -static int ks_pcie_am654_set_mode(struct device *dev) +static int ks_pcie_am654_set_mode(struct device *dev, + enum dw_pcie_device_mode mode) { struct device_node *np = dev->of_node; struct regmap *syscon; @@ -936,7 +1075,18 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; mask = AM654_PCIE_DEV_TYPE_MASK; - val = RC; + + switch (mode) { + case DW_PCIE_RC_TYPE: + val = RC; + break; + case DW_PCIE_EP_TYPE: + val = EP; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + return -EINVAL; + } ret = regmap_update_bits(syscon, 0, mask, val); if (ret) { @@ -954,6 +1104,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = { static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { .host_ops = &ks_pcie_am654_host_ops, + .mode = DW_PCIE_RC_TYPE, + .version = 0x490A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { + .ep_ops = &ks_pcie_am654_ep_ops, + .mode = DW_PCIE_EP_TYPE, .version = 0x490A, }; @@ -967,16 +1124,22 @@ static const struct of_device_id ks_pcie_of_match[] = { .data = &ks_pcie_am654_rc_of_data, .compatible = "ti,am654-pcie-rc", }, + { + .data = &ks_pcie_am654_ep_of_data, + .compatible = "ti,am654-pcie-ep", + }, { }, }; static int __init ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; const struct ks_pcie_of_data *data; const struct of_device_id *match; + enum dw_pcie_device_mode mode; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; @@ -999,6 +1162,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) version = data->version; host_ops = data->host_ops; + ep_ops = data->ep_ops; + mode = data->mode; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -1021,16 +1186,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return PTR_ERR(base); pci->dbi_base = base; + pci->dbi_base2 = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; pci->version = version; - ret = of_property_read_u32(np, "num-viewport", &num_viewport); - if (ret < 0) { - dev_err(dev, "unable to read *num-viewport* property\n"); - return ret; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource: %d\n", irq); @@ -1079,7 +1239,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->pci = pci; ks_pcie->link = link; ks_pcie->num_lanes = num_lanes; - ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; ret = ks_pcie_enable_phy(ks_pcie); @@ -1106,7 +1265,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->atu_base = atu_base; - ret = ks_pcie_am654_set_mode(dev); + ret = ks_pcie_am654_set_mode(dev, mode); if (ret < 0) goto err_get_sync; } else { @@ -1115,10 +1274,39 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - pci->pp.ops = host_ops; - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); - if (ret < 0) - goto err_get_sync; + switch (mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + ret = of_property_read_u32(np, "num-viewport", &num_viewport); + if (ret < 0) { + dev_err(dev, "unable to read *num-viewport* property\n"); + return ret; + } + + ks_pcie->num_viewport = num_viewport; + pci->pp.ops = host_ops; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + pci->ep.ops = ep_ops; + ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } ks_pcie_enable_error_irq(ks_pcie);

[20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms

Commit Message

Patch