From patchwork Mon Mar 25 08:34:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 10868347 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45C0A18A6 for ; Mon, 25 Mar 2019 08:39:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 330CF28F72 for ; Mon, 25 Mar 2019 08:39:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2521F28F8D; Mon, 25 Mar 2019 08:39:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AEA428BAB for ; Mon, 25 Mar 2019 08:39:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730089AbfCYIg2 (ORCPT ); Mon, 25 Mar 2019 04:36:28 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54822 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729965AbfCYIg1 (ORCPT ); Mon, 25 Mar 2019 04:36:27 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aCpZ106411; Mon, 25 Mar 2019 03:36:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502972; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=azTQ0AGmsp4+BAkPd/6ewSMKH63GZ0o5P4D6DseFRL5X6k7/6OK84uARHwhUGvdM9 GNrFSEWe+s+zEKD3utzivbVQQDYQF/I615Q+dDOmZyWnimnOIqkqyJ2D+1cwVoabV3 3rVetJZ8kBOnVeVUSXpbQiArpNw2S3Y47XQYVbOg= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aBWu091356 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:11 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:11 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFj006534; Mon, 25 Mar 2019 03:36:07 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 03/26] dt-bindings: PCI: keystone: Add "reg-names" binding information Date: Mon, 25 Mar 2019 14:04:38 +0530 Message-ID: <20190325083501.8088-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add "reg-names" binding information in order for device tree node to be populated with the correct register strings. This will break old dt compatibility. However Keystone PCI has never worked in upstream kernel due to lack of SERDES support. Before SERDES support is added, cleanup the Keystone PCI dt-bindngs. This new binding will also be used by PCI in AM654 platform. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1