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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id i3sm17418026ion.9.2019.08.21.05.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2019 05:55:22 -0700 (PDT) From: Adam Ford To: linux-omap@vger.kernel.org Cc: adam.ford@logicpd.com, tony@atomide.com, Adam Ford , =?utf-8?q?Filip_Matijevi=C4=87?= , "H. Nikolaus Schaller" , Ivaylo Dimitrov , moaz korena , Merlijn Wajer , =?utf-8?q?Pawe=C5=82_Chmiel?= , Philipp Rossak , Tomi Valkeinen Subject: [PATCH] ARM: dts: Configure rstctrl reset for SGX on AM3517 Date: Wed, 21 Aug 2019 07:55:02 -0500 Message-Id: <20190821125502.32187-1-aford173@gmail.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Based on Tony Lindgren's work for omap34xx, this patch applies the same functionality to the AM3517. The following can be tested via sysfs with the following to ensure the SGX module gets enabled and disabled properly: 0x00010201 Bus error Note that this patch depends on the PRM rstctrl driver that has been recently posted. If the child device driver(s) need to prevent rstctrl reset on PM runtime suspend, the drivers need to increase the usecount for the shared rstctrl reset that can be mapped also for the child device(s) or accessed via dev->parent. Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Adam Ford diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 23ea381d363f..bf3002009b00 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -88,6 +88,30 @@ interrupts = <24>; clocks = <&hecc_ck>; }; + + /* + * On am3517 the OCP registers do not seem to be accessible + * similar to the omap34xx. Maybe SGX is permanently set to + * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is + * write-only at 0x50000e10. We detect SGX based on the SGX + * revision register instead of the unreadable OCP revision + * register. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000014 0x4>; + reg-names = "rev"; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; }; };