From patchwork Wed Aug 28 07:19:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F324D184E for ; Wed, 28 Aug 2019 07:20:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D22D3217F5 for ; Wed, 28 Aug 2019 07:20:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="LraKS8Tz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726301AbfH1HUF (ORCPT ); Wed, 28 Aug 2019 03:20:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33448 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbfH1HUF (ORCPT ); Wed, 28 Aug 2019 03:20:05 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JsW1126646; Wed, 28 Aug 2019 02:19:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976794; bh=4/vn3nShvBSwpELcXgs5bhAcnH64+34+9f0PSBWUDWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LraKS8TzgEzeYPHL4snMeE1o84L1wckgIsDr7E6wpgeU5JfDuCio95vxBJ+W4EcHp uHfalLNWZHAaRjdkaub4waGf9pv9M8ZaaQiMFO1vVP+d17PfmzDODyFRup8BrF2JKi wo2Cz+w2REE1unixyoxLKytENSJoyyrLIZr6xtmo= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Js4E025032 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:54 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:53 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:53 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfD052201; Wed, 28 Aug 2019 02:19:51 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 01/11] dt-bindings: omap: add new binding for PRM instances Date: Wed, 28 Aug 2019 10:19:31 +0300 Message-ID: <20190828071941.32378-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo --- .../devicetree/bindings/arm/omap/prm-inst.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..7c7527c37734 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,31 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must be one of: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. +- clocks: Associated clocks for the reset signals if any. Certain reset + signals can't be toggled properly without functional clock + being active for them. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +};