From patchwork Wed Aug 28 07:56:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA4B51398 for ; Wed, 28 Aug 2019 07:57:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB95D22CF8 for ; Wed, 28 Aug 2019 07:57:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fpx+YKcp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726290AbfH1H5J (ORCPT ); Wed, 28 Aug 2019 03:57:09 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:37170 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726422AbfH1H5J (ORCPT ); Wed, 28 Aug 2019 03:57:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v5ms127667; Wed, 28 Aug 2019 02:57:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979025; bh=bV7v6jpzGIFR9zq5s75cVQi0wC5i+NfYYrnSlvWqJrY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fpx+YKcpik5O8NsYVVQvNBBcj20qZLch66ErL87bPypPTB/oqDBgy1OL2ByrUmy1i Te8W7NMdmak1u5aFyVkYqiW4GUeGjdbD9QGnUM+LFKGatBpcJxkHgViGoIdOrMimdi qlp/l7MCOg5a+f4kJdu+w06HuDehryacpQbV8/aY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v5c7127606 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:05 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:04 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:04 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFo107124; Wed, 28 Aug 2019 02:57:03 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 05/10] ARM: dts: am43xx: Add PRM data Date: Wed, 28 Aug 2019 10:56:39 +0300 Message-ID: <20190828075644.4493-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM data for AM43xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am4372.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 55aff4db9c7c..4bd22c6ba3ff 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -353,3 +353,32 @@ #include "am437x-l4.dtsi" #include "am43xx-clocks.dtsi" + +&prcm { + prm_gfx: prm@400 { + compatible = "ti,am4-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; + }; + + prm_per: prm@800 { + compatible = "ti,am4-prm-inst"; + reg = <0x800 0x100>; + #reset-cells = <1>; + clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; + }; + + prm_wkup: prm@2000 { + compatible = "ti,am4-prm-inst"; + reg = <0x2000 0x100>; + #reset-cells = <1>; + clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; + }; + + prm_device: prm@4000 { + compatible = "ti,am4-prm-inst"; + reg = <0x4000 0x100>; + #reset-cells = <1>; + }; +};