| Message ID | 20190905161759.28036-5-mathieu.poirier@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Backport candidate from TI 4.14 product kernel | expand |
On Thu, Sep 05, 2019 at 10:17:45AM -0600, Mathieu Poirier wrote: > From: Roger Quadros <rogerq@ti.com> > > commit 42bf02ec6e420e541af9a47437d0bdf961ca2972 upstream > > Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble > with the metastability workaround as it supports only > a High-Speed PHY and the PHY can enter into an Erratic state [1] > when the controller is set in SuperSpeed mode as part of > the metastability workaround. > > This causes upto 2 seconds delay in enumeration on DRA7's USB2 > instance in gadget mode. > > If these platforms can be better off without the workaround, > provide a device tree property to suggest that so the workaround > is avoided. > > [1] Device mode enumeration trace showing PHY Erratic Error. > irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0] > irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0] > irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0] Does the DT also need to get updated with this new id for this? Is that a separate patch somewhere? thanks, greg k-h
On Tue, 10 Sep 2019 at 08:36, Greg KH <greg@kroah.com> wrote: > > On Thu, Sep 05, 2019 at 10:17:45AM -0600, Mathieu Poirier wrote: > > From: Roger Quadros <rogerq@ti.com> > > > > commit 42bf02ec6e420e541af9a47437d0bdf961ca2972 upstream > > > > Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble > > with the metastability workaround as it supports only > > a High-Speed PHY and the PHY can enter into an Erratic state [1] > > when the controller is set in SuperSpeed mode as part of > > the metastability workaround. > > > > This causes upto 2 seconds delay in enumeration on DRA7's USB2 > > instance in gadget mode. > > > > If these platforms can be better off without the workaround, > > provide a device tree property to suggest that so the workaround > > is avoided. > > > > [1] Device mode enumeration trace showing PHY Erratic Error. > > irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0] > > irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0] > > irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0] > > Does the DT also need to get updated with this new id for this? Is that > a separate patch somewhere? The upstream commit is: b8c9c6fa2002 ARM: dts: dra7: Disable USB metastability workaround for USB2 Should I just send the latter or you prefer a resend with both patches? Thanks, Mathieu > > thanks, > > greg k-h
On Wed, Sep 11, 2019 at 08:01:40AM -0600, Mathieu Poirier wrote: > On Tue, 10 Sep 2019 at 08:36, Greg KH <greg@kroah.com> wrote: > > > > On Thu, Sep 05, 2019 at 10:17:45AM -0600, Mathieu Poirier wrote: > > > From: Roger Quadros <rogerq@ti.com> > > > > > > commit 42bf02ec6e420e541af9a47437d0bdf961ca2972 upstream > > > > > > Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble > > > with the metastability workaround as it supports only > > > a High-Speed PHY and the PHY can enter into an Erratic state [1] > > > when the controller is set in SuperSpeed mode as part of > > > the metastability workaround. > > > > > > This causes upto 2 seconds delay in enumeration on DRA7's USB2 > > > instance in gadget mode. > > > > > > If these platforms can be better off without the workaround, > > > provide a device tree property to suggest that so the workaround > > > is avoided. > > > > > > [1] Device mode enumeration trace showing PHY Erratic Error. > > > irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0] > > > irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0] > > > irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0] > > > > Does the DT also need to get updated with this new id for this? Is that > > a separate patch somewhere? > > The upstream commit is: > > b8c9c6fa2002 ARM: dts: dra7: Disable USB metastability workaround for USB2 > > Should I just send the latter or you prefer a resend with both patches? I've queued this up now, along with the rest of this series, thanks. greg k-h
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 52fb41046b34..44e8bab159ad 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -47,6 +47,8 @@ Optional properties: from P0 to P1/P2/P3 without delay. - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check during HS transmit. + - snps,dis_metastability_quirk: when set, disable metastability workaround. + CAUTION: use only if you are absolutely sure of it. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 945330ea8d5c..9b093978bd24 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1115,6 +1115,9 @@ static void dwc3_get_properties(struct dwc3 *dwc) device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj); + dwc->dis_metastability_quirk = device_property_read_bool(dev, + "snps,dis_metastability_quirk"); + dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index abd1142c9e4d..40bf0e0768d9 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -869,6 +869,7 @@ struct dwc3_scratchpad_array { * 1 - -3.5dB de-emphasis * 2 - No de-emphasis * 3 - Reserved + * @dis_metastability_quirk: set to disable metastability quirk. * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. */ @@ -1025,6 +1026,8 @@ struct dwc3 { unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; + unsigned dis_metastability_quirk:1; + u16 imod_interval; }; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 1b99d44e52b9..5916340c4162 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2034,7 +2034,8 @@ static void dwc3_gadget_set_speed(struct usb_gadget *g, * STAR#9000525659: Clock Domain Crossing on DCTL in * USB 2.0 Mode */ - if (dwc->revision < DWC3_REVISION_220A) { + if (dwc->revision < DWC3_REVISION_220A && + !dwc->dis_metastability_quirk) { reg |= DWC3_DCFG_SUPERSPEED; } else { switch (speed) { @@ -3265,7 +3266,8 @@ int dwc3_gadget_init(struct dwc3 *dwc) * is less than super speed because we don't have means, yet, to tell * composite.c that we are USB 2.0 + LPM ECN. */ - if (dwc->revision < DWC3_REVISION_220A) + if (dwc->revision < DWC3_REVISION_220A && + !dwc->dis_metastability_quirk) dev_info(dwc->dev, "changing max_speed on rev %08x\n", dwc->revision);