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[80.200.33.241]) by smtp.gmail.com with ESMTPSA id d19sm3891496wmd.38.2019.12.06.08.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2019 08:00:24 -0800 (PST) From: Jean Pihet To: Mark Brown , Tero Kristo Cc: linux-omap@vger.kernel.org, linux-spi@vger.kernel.org, Ryan Barnett , Conrad Ratschan , Jean Pihet Subject: [PATCH 2/3] TI QSPI: support large flash devices Date: Fri, 6 Dec 2019 17:00:06 +0100 Message-Id: <20191206160007.331801-3-jean.pihet@newoldbits.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191206160007.331801-1-jean.pihet@newoldbits.com> References: <20191206160007.331801-1-jean.pihet@newoldbits.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The TI QSPI IP has limitations: - the MMIO region is 64MB in size - in non-MMIO mode, the transfer can handle 4096 words max. Add support for bigger devices. Use MMIO and DMA transfers below the 64MB boundary, use software generated transfers above. --- drivers/spi/spi-ti-qspi.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 4680dad38ab2..13916232a959 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -524,6 +524,33 @@ static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode, QSPI_SPI_SETUP_REG(spi->chip_select)); } +static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) +{ + struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master); + size_t max_len; + + if (op->data.dir == SPI_MEM_DATA_IN) { + if (op->addr.val < qspi->mmap_size) { + /* Limit MMIO to the mmaped region */ + if (op->addr.val + op->data.nbytes > qspi->mmap_size) { + max_len = qspi->mmap_size - op->addr.val; + op->data.nbytes = min(op->data.nbytes, max_len); + } + } else { + /* + * Use fallback mode (SW generated transfers) above the + * mmaped region. + * Adjust size to comply with the QSPI max frame length. + */ + max_len = QSPI_FRAME * op->data.buswidth; + max_len -= 1 + op->addr.nbytes + op->dummy.nbytes; + op->data.nbytes = min(op->data.nbytes, max_len); + } + } + + return 0; +} + static int ti_qspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -574,6 +601,7 @@ static int ti_qspi_exec_mem_op(struct spi_mem *mem, static const struct spi_controller_mem_ops ti_qspi_mem_ops = { .exec_op = ti_qspi_exec_mem_op, + .adjust_op_size = ti_qspi_adjust_op_size, }; static int ti_qspi_start_transfer_one(struct spi_master *master, @@ -599,12 +627,11 @@ static int ti_qspi_start_transfer_one(struct spi_master *master, frame_len_words = 0; list_for_each_entry(t, &m->transfers, transfer_list) frame_len_words += t->len / (t->bits_per_word >> 3); - frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME); /* setup command reg */ qspi->cmd = 0; qspi->cmd |= QSPI_EN_CS(spi->chip_select); - qspi->cmd |= QSPI_FLEN(frame_len_words); + qspi->cmd |= QSPI_FLEN(QSPI_FRAME); ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);