From patchwork Fri Feb 28 09:53:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 11411933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1DDC213A4 for ; Fri, 28 Feb 2020 09:55:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F15E8246AF for ; Fri, 28 Feb 2020 09:55:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="x57eq40q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726975AbgB1JzR (ORCPT ); Fri, 28 Feb 2020 04:55:17 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46234 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726838AbgB1JzG (ORCPT ); Fri, 28 Feb 2020 04:55:06 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 01S9sqIx094304; Fri, 28 Feb 2020 03:54:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1582883692; bh=FGTSQLyt4Rs2yRXyN5TRTiV34kGpB4c6H54YyVHcPuk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x57eq40qjAekJ6El4rdjfJeVUmDtQv0w0c3pspfNGd+bu64ps3CvEcSlM7WDiU/33 OnAokfC7EFfmOAiCOdWclClLgunaNOf0yRNPKQ86jF9Gxtsgb3KeaOegVmkKCOOKIc fhHKxtBxl5zHOYv9mxuEQ6+HOIaaPTiiEtzAvq9Q= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 01S9sqd1026108 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Feb 2020 03:54:52 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 28 Feb 2020 03:54:52 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 28 Feb 2020 03:54:52 -0600 Received: from uda0131933.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 01S9sbB6125348; Fri, 28 Feb 2020 03:54:49 -0600 From: Lokesh Vutla To: Tony Lindgren , Daniel Lezcano , Thomas Gleixner CC: Linux OMAP Mailing List , , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , , Sekhar Nori , Tero Kristo , Lokesh Vutla , Tony Lindgren Subject: [PATCH v2 3/5] clocksource: timer-ti-dm: Do not update counter on updating the period Date: Fri, 28 Feb 2020 15:23:44 +0530 Message-ID: <20200228095346.32177-4-lokeshvutla@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200228095346.32177-1-lokeshvutla@ti.com> References: <20200228095346.32177-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Write to trigger register(OMAP_TIMER_TRIGGER_REG) will load the value in Load register(OMAP_TIMER_LOAD_REG) into Counter register (OMAP_TIMER_COUNTER_REG). omap_dm_timer_set_load() writes into trigger register every time load register is updated. When timer is configured in pwm mode, this causes disruption in current pwm cycle, which is not expected especially when pwm is used as PPS signal for synchronized PTP clocks. So do not write into trigger register on updating the period. Tested-by: Tony Lindgren Signed-off-by: Lokesh Vutla --- drivers/clocksource/timer-ti-dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c index 9606103b92e0..4c32ee41339a 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -544,7 +544,6 @@ static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); - omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); omap_dm_timer_disable(timer); return 0; }