diff mbox series

[RFC,23/27] PCI: dwc/meson: Drop unnecessary RC config space initialization

Message ID 20200803210116.3132633-24-robh@kernel.org (mailing list archive)
State New, archived
Headers show
Series PCI: dwc: Driver clean-ups | expand

Commit Message

Rob Herring (Arm) Aug. 3, 2020, 9:01 p.m. UTC 
The common Designware init already initializes the RC PCI_COMMAND, BAR0
and BAR1 registers.

The only difference here is the common code sets SERR. If clearing SERR
is what's desired, then the Meson driver should do that instead.

Cc: Yue Wang <yue.wang@Amlogic.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pci-meson.c | 20 --------------------
 1 file changed, 20 deletions(-)
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index cbde683d107f..d1cfc65f0a69 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -34,15 +34,6 @@ 
 #define NUM_OF_LANES_X1			BIT(8)
 #define DIRECT_SPEED_CHANGE		BIT(17)
 
-#define TYPE1_HDR_OFFSET		0x0
-#define PCIE_STATUS_COMMAND		(TYPE1_HDR_OFFSET + 0x04)
-#define PCI_IO_EN			BIT(0)
-#define PCI_MEM_SPACE_EN		BIT(1)
-#define PCI_BUS_MASTER_EN		BIT(2)
-
-#define PCIE_BASE_ADDR0			(TYPE1_HDR_OFFSET + 0x10)
-#define PCIE_BASE_ADDR1			(TYPE1_HDR_OFFSET + 0x14)
-
 #define PCIE_CAP_OFFSET			0x70
 #define PCIE_DEV_CTRL_DEV_STUS		(PCIE_CAP_OFFSET + 0x08)
 #define PCIE_CAP_MAX_PAYLOAD_MASK	GENMASK(7, 5)
@@ -303,9 +294,6 @@  static void meson_pcie_init_dw(struct meson_pcie *mp)
 	val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
 	val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
 	meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
-
-	meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
-	meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
 }
 
 static int meson_size_to_payload(struct meson_pcie *mp, int size)
@@ -353,13 +341,6 @@  static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
 	meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
 }
 
-static inline void meson_enable_memory_space(struct meson_pcie *mp)
-{
-	/* Set the RC Bus Master, Memory Space and I/O Space enables */
-	meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
-			 PCIE_STATUS_COMMAND);
-}
-
 static int meson_pcie_establish_link(struct meson_pcie *mp)
 {
 	struct dw_pcie *pci = &mp->pci;
@@ -370,7 +351,6 @@  static int meson_pcie_establish_link(struct meson_pcie *mp)
 	meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
 
 	dw_pcie_setup_rc(pp);
-	meson_enable_memory_space(mp);
 
 	meson_pcie_assert_reset(mp);