From patchwork Mon Apr 12 14:07:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12198201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 958CCC43461 for ; Mon, 12 Apr 2021 14:07:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 703F36128B for ; Mon, 12 Apr 2021 14:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242029AbhDLOH5 (ORCPT ); Mon, 12 Apr 2021 10:07:57 -0400 Received: from mga05.intel.com ([192.55.52.43]:33978 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238015AbhDLOH4 (ORCPT ); Mon, 12 Apr 2021 10:07:56 -0400 IronPort-SDR: l2mWL90mY2042G82W3E6yK+L9W9Ba3UaQkmU4rIIxkK8chO+/4KIRAHQhG+ACVQnc3vzKCxxIp ebuN1p5lW1Xw== X-IronPort-AV: E=McAfee;i="6200,9189,9952"; a="279498533" X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="279498533" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 07:07:38 -0700 IronPort-SDR: Uo/sEmcUcwbPsjlWzDghuO/w6fR1yobrChD3JGkkh4PQQTm523NkKotcnWb1LpjrcLtol4DiNp g7tRSdUb1GaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="531890655" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 12 Apr 2021 07:07:33 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id DC02512A; Mon, 12 Apr 2021 17:07:49 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , "Gustavo A. R. Silva" , Linus Walleij , Drew Fustini , Tony Lindgren , Christophe JAILLET , Thierry Reding , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, linux-tegra@vger.kernel.org Cc: Vladimir Zapolskiy , Haojian Zhuang , Michal Simek , Daniel Mack , Robert Jarzmik , Thierry Reding , Jonathan Hunter Subject: [PATCH v1 1/3] pinctrl: Keep enum pin_config_param ordered by name Date: Mon, 12 Apr 2021 17:07:39 +0300 Message-Id: <20210412140741.39946-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org It seems the ordering is by name. Keep it that way. Signed-off-by: Andy Shevchenko --- include/linux/pinctrl/pinconf-generic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 6aeb711f7cd1..188db8d84162 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -90,6 +90,7 @@ struct pinctrl_map; * value on the line. Use argument 1 to indicate high level, argument 0 to * indicate low level. (Please see Documentation/driver-api/pinctl.rst, * section "GPIO mode pitfalls" for a discussion around this parameter.) + * @PIN_CONFIG_PERSIST_STATE: retain pin state across sleep or controller reset * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power * supplies, the argument to this parameter (on a custom format) tells * the driver which alternative power source to use. @@ -101,7 +102,6 @@ struct pinctrl_map; * or latch delay (on outputs) this parameter (in a custom format) * specifies the clock skew or latch delay. It typically controls how * many double inverters are put in front of the line. - * @PIN_CONFIG_PERSIST_STATE: retain pin state across sleep or controller reset * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if * you need to pass in custom configurations to the pin controller, use * PIN_CONFIG_END+1 as the base offset. @@ -127,11 +127,11 @@ enum pin_config_param { PIN_CONFIG_LOW_POWER_MODE, PIN_CONFIG_OUTPUT_ENABLE, PIN_CONFIG_OUTPUT, + PIN_CONFIG_PERSIST_STATE, PIN_CONFIG_POWER_SOURCE, PIN_CONFIG_SLEEP_HARDWARE_STATE, PIN_CONFIG_SLEW_RATE, PIN_CONFIG_SKEW_DELAY, - PIN_CONFIG_PERSIST_STATE, PIN_CONFIG_END = 0x7F, PIN_CONFIG_MAX = 0xFF, };