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Niedermayr" To: , CC: , , , Subject: [PATCH v3 2/3] memory: omap-gpmc: add support for wait pin polarity Date: Tue, 6 Sep 2022 14:47:44 +0200 Message-ID: <20220906124747.1767318-3-benedikt.niedermayr@siemens.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906124747.1767318-1-benedikt.niedermayr@siemens.com> References: <20220906124747.1767318-1-benedikt.niedermayr@siemens.com> MIME-Version: 1.0 X-Originating-IP: [139.23.126.196] X-ClientProxiedBy: DEMCHDC89XA.ad011.siemens.net (139.25.226.103) To DEMCHDC8A0A.ad011.siemens.net (139.25.226.106) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a8b7393-c3d6-471c-3646-08da90060661 X-MS-TrafficTypeDiagnostic: AS8PR10MB6248:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3q0jYayDT9zvrh4gupkM7ssMIjGIbQRbcvi4DmW0vHMl1dnOooxr/PBn6w7eWBaFb77SxYIv3Ae4yHuDWmdyRZqsNsbOqEVfRxyHhh/4b7vSdXOa3YYGkb+6diup6ny/CdNEsMF+KcWdyfN2vF8/PELj2xa6nbI1N9eu28/Yd4nCb/na1G0/c3kq7fj156/j4KTqluStr1OdlNHtxPOX8mRT6YDCHBBTM1ohTIXvsfcoVW201+WZazk/h1o7G6lNfWm+LFyp+X//yF/X6393wPFe9jt9xzum/erZeai5K/LtjgqTXdhs6kNsfEnfj5bz2a7gUc0T5/sl8Os51hY8x9NjPzk2WZfLXgGtuQU5k81RePk47Kbu4xlmZGpQpsvSw+/ogft2MNxDZ9yfusW5VmZ+O2ryW6gXwDKTwfJpfGGU+WtFZiKmGW58qYNha7Hp6KXCIR/6pOfc5o5nneDZTHRbkAvXgt4RrAg/fuVnFZh6GLBPLI7Oilw+XuYfUmeK6dBeA5LmMjawHvEyKfJuIogKomNhBzWNAcgthsFLyAMlZA7Xjeu5pDmzJIcM2TW765tdXlHE33tKaZxrG2encQR3yaIW/3lHifZChMUjhQpsoGimBWo9c7GgOkzdgtQB0bZaBD3fkVnG3PXFqCx1aPMwoFO7LzAZ9luz8gPI94e5oYAvqT7t/bS3tlfVwx52vMpNK35XXucsbILGgB4lYgCApljmT5N8RS4co2zROaSsUbLuKl8A36dg5JCsP00cnLCBviaI0gVyZP2mIjpzWw== X-Forefront-Antispam-Report: CIP:194.138.21.74;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:hybrid.siemens.com;PTR:hybrid.siemens.com;CAT:NONE;SFS:(13230016)(4636009)(346002)(376002)(396003)(136003)(39860400002)(40470700004)(36840700001)(46966006)(7636003)(36860700001)(8676002)(356005)(7596003)(4326008)(82960400001)(70206006)(70586007)(82740400003)(2616005)(1076003)(186003)(47076005)(41300700001)(16526019)(336012)(956004)(40460700003)(110136005)(6666004)(54906003)(316002)(26005)(8936002)(86362001)(478600001)(5660300002)(2906002)(40480700001)(82310400005)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2022 12:47:57.7050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a8b7393-c3d6-471c-3646-08da90060661 X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a;Ip=[194.138.21.74];Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR01FT099.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB6248 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Benedikt Niedermayr The waitpin polarity can be configured via the WAITPINPOLARITY bits in the GPMC_CONFIG register. This is currently not supported by the driver. This patch adds support for setting the required register bits with the "gpmc,wait-pin-active-low" device tree property. Signed-off-by: Benedikt Niedermayr --- drivers/memory/omap-gpmc.c | 15 +++++++++++++++ include/linux/platform_data/gpmc-omap.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index e3674a15b934..609df21e0ce6 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -132,6 +132,7 @@ #define GPMC_CONFIG_DEV_SIZE 0x00000002 #define GPMC_CONFIG_DEV_TYPE 0x00000003 +#define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) @@ -1881,6 +1882,18 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); + if (p->wait_on_read || p->wait_on_write) { + config1 = gpmc_read_reg(GPMC_CONFIG); + + if (p->wait_pin_active_low) + config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); + else + config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); + + gpmc_write_reg(GPMC_CONFIG, config1); + } + + return 0; } @@ -1985,6 +1998,8 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) "gpmc,wait-on-read"); p->wait_on_write = of_property_read_bool(np, "gpmc,wait-on-write"); + p->wait_pin_active_low = of_property_read_bool(np, + "gpmc,wait-pin-active-low"); if (!p->wait_on_read && !p->wait_on_write) pr_debug("%s: rd/wr wait monitoring not enabled!\n", __func__); diff --git a/include/linux/platform_data/gpmc-omap.h b/include/linux/platform_data/gpmc-omap.h index c9cc4e32435d..7c9675165e8a 100644 --- a/include/linux/platform_data/gpmc-omap.h +++ b/include/linux/platform_data/gpmc-omap.h @@ -149,6 +149,7 @@ struct gpmc_settings { u32 device_width; /* device bus width (8 or 16 bit) */ u32 mux_add_data; /* multiplex address & data */ u32 wait_pin; /* wait-pin to be used */ + bool wait_pin_active_low; /* wait-pin polarity */ }; /* Data for each chip select */