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Niedermayr" To: , CC: , , , Subject: [PATCH v4 2/3] memory: omap-gpmc: add support for wait pin polarity Date: Thu, 15 Sep 2022 11:13:32 +0200 Message-ID: <20220915091333.2425306-3-benedikt.niedermayr@siemens.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915091333.2425306-1-benedikt.niedermayr@siemens.com> References: <20220915091333.2425306-1-benedikt.niedermayr@siemens.com> MIME-Version: 1.0 X-Originating-IP: [144.145.220.66] X-ClientProxiedBy: DEMCHDC8A0A.ad011.siemens.net (139.25.226.106) To DEMCHDC8A0A.ad011.siemens.net (139.25.226.106) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HE1EUR01FT070:EE_|AS4PR10MB6088:EE_ X-MS-Office365-Filtering-Correlation-Id: f1f74f1f-3133-4f03-51ce-08da96fa976e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zlp9nuFmrxxnIfS4ddUTB2UMWGSn59iJm1sXXKDqvWtQY7MCNvNmgnV01Y8faMlwPcHzYK2PLMsSj2w4bwGo/x/B8pf9S5Lv7prAYlv8sw7jc8gI/QvfhI1yTABvpOCaOthJjNWKbB/oGpcblnfPMcJY3PBm+dH+18SAEIV9VRK5NGwk+wKpLV6Lvn69DbVnq/cIuiSqec9VxRQVmOqJQcO6w0Wj06rt/L2/QEmOjCMW5E9xAAqhWaAT6LfpiDKOGOVL59g17XZstgP1KTGMdluSH6ToC0fI6UHNrmOibsZOG4kpE5VPdRYFduIynJrJG4tWvZ98HSzaBEKGDst1Vx/OPQUpfOd+sNAFUjBOjW5YMPYFSMKBTetZyLLm5aJVrt82KXjOEOg3cS0RN4fGPQIUlnGVoiwEL51XAhnViCANnnLw8d8D36am+a43QLxjc9ehMoQv2pqOccKtm6HBaYPhSj8yd/PIuCKvjSN3Oc+NckWZ4wizkv5JHlSy/PUUqiDW1t7P94Mjk7OsWoAYkchgMLfU6nOLdczuS8/VmKxFb/1gqPvPthxBGtSmLqCJ+w5O8Z0B3nXCy7xgQrIE92iYXXbKpypM53bwzxmlPS81Jwe1IQlw4QdyACQ/S7zXNOYUYAmDOmYHkQYOXfXWBgUeNZFianJ+ZllYeqNHrkn9MrjxL9+1+ba4oRWzLF410bW8P/5Nn4KulOIw4YUPMM6jA0lc86oVBZAnxXp3alMQVpF6EPvHLKfICw81LU0Eto08xlRqmkP4R6WBpHAQFg== X-Forefront-Antispam-Report: CIP:194.138.21.74;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:hybrid.siemens.com;PTR:hybrid.siemens.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(39860400002)(396003)(346002)(451199015)(36840700001)(46966006)(40470700004)(186003)(40460700003)(82960400001)(82740400003)(356005)(7636003)(6666004)(7596003)(16526019)(336012)(70586007)(2616005)(956004)(1076003)(2906002)(478600001)(5660300002)(82310400005)(36860700001)(8676002)(70206006)(26005)(4326008)(47076005)(8936002)(110136005)(54906003)(86362001)(36756003)(316002)(40480700001)(41300700001);DIR:OUT;SFP:1101; X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2022 09:13:45.1832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1f74f1f-3133-4f03-51ce-08da96fa976e X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a;Ip=[194.138.21.74];Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: HE1EUR01FT070.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR10MB6088 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Benedikt Niedermayr The waitpin polarity can be configured via the WAITPINPOLARITY bits in the GPMC_CONFIG register. This is currently not supported by the driver. This patch adds support for setting the required register bits with the "gpmc,wait-pin-polarity" dt-property. Signed-off-by: Benedikt Niedermayr --- drivers/memory/omap-gpmc.c | 22 ++++++++++++++++++++++ include/linux/platform_data/gpmc-omap.h | 6 ++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index e3674a15b934..66dd7dd80653 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -132,6 +132,7 @@ #define GPMC_CONFIG_DEV_SIZE 0x00000002 #define GPMC_CONFIG_DEV_TYPE 0x00000003 +#define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) @@ -1881,6 +1882,21 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); + if (p->wait_on_read || p->wait_on_write) { + config1 = gpmc_read_reg(GPMC_CONFIG); + + if (p->wait_pin_polarity == WAITPINPOLARITY_ACTIVE_LOW) + config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); + else if (p->wait_pin_polarity == WAITPINPOLARITY_ACTIVE_HIGH) + config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); + else if (p->wait_pin_polarity != WAITPINPOLARITY_DEFAULT) + pr_err("%s: invalid wait-pin-polarity (pin: %d, polarity: %d)\n", + __func__, p->wait_pin, p->wait_pin_polarity); + + gpmc_write_reg(GPMC_CONFIG, config1); + } + + return 0; } @@ -1981,6 +1997,12 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) } if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { + + p->wait_pin_polarity = WAITPINPOLARITY_DEFAULT; + of_property_read_u32(np, + "gpmc,wait-pin-polarity", + &p->wait_pin_polarity); + p->wait_on_read = of_property_read_bool(np, "gpmc,wait-on-read"); p->wait_on_write = of_property_read_bool(np, diff --git a/include/linux/platform_data/gpmc-omap.h b/include/linux/platform_data/gpmc-omap.h index c9cc4e32435d..c46c28069c31 100644 --- a/include/linux/platform_data/gpmc-omap.h +++ b/include/linux/platform_data/gpmc-omap.h @@ -136,6 +136,11 @@ struct gpmc_device_timings { #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ #define GPMC_MUX_AD 2 /* Addr-Data multiplex */ +/* Wait pin polarity values */ +#define WAITPINPOLARITY_DEFAULT -1 +#define WAITPINPOLARITY_ACTIVE_LOW 0 +#define WAITPINPOLARITY_ACTIVE_HIGH 1 + struct gpmc_settings { bool burst_wrap; /* enables wrap bursting */ bool burst_read; /* enables read page/burst mode */ @@ -149,6 +154,7 @@ struct gpmc_settings { u32 device_width; /* device bus width (8 or 16 bit) */ u32 mux_add_data; /* multiplex address & data */ u32 wait_pin; /* wait-pin to be used */ + u32 wait_pin_polarity; /* wait-pin polarity */ }; /* Data for each chip select */