From patchwork Tue Sep 27 08:35:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jerome Neanne X-Patchwork-Id: 12990156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 977B8C6FA86 for ; Tue, 27 Sep 2022 08:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231185AbiI0IgT (ORCPT ); Tue, 27 Sep 2022 04:36:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231674AbiI0Ifq (ORCPT ); Tue, 27 Sep 2022 04:35:46 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF46913F8A for ; Tue, 27 Sep 2022 01:35:32 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id z13-20020a7bc7cd000000b003b5054c6f9bso8435523wmk.2 for ; Tue, 27 Sep 2022 01:35:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=zGKP5Wt8s+Izp0RT7HfI6dIBI6KAZhMJfhNjmmY98W4=; b=0XDh4L75n5xM9BkHE0spGrEwDZGqdf2onTMdk+Rx72eXKp09Az3+KL7A2C2uXRrBoj f6k8dHuN0lmSONofNLBIDvxVPKaTkw3i9l10LHI4qI3lhw1hTmBhoNMz/uUImt9cZtit CX1ijEcZn2v9tY/TeZGcuPjYS1qvdz2C6p7tzqBkvcBX/L0GQ0kvjW2KjAfzfkXs3iHH hAQJb2tIAdUvEsN+31+ZIlVi8YiZeA4gcVSbChNoClrxfWmpzKVfuQ/XMyuGAs7jHiju 8XFNQo0FeqF97auKMdqM3GBQ03Ei8uSkzE87QGkSU/GrW8CyNfjn+c+O2kmIUPBzw/4M d2jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=zGKP5Wt8s+Izp0RT7HfI6dIBI6KAZhMJfhNjmmY98W4=; b=b2ZTbrNYz/AU5WAXIC0WCxHFBCcMvla13365bGH+7i4/4wdXZHzid385S5t58oryJW rNTM1tuxuPd2HiOJO6S3WfcHs1sfpd5PHOKHDIvb8PSu1BAytuSCgT+PZk+bDs0HqRaP 3ksvWmbKmRmG5Qx7xIGEnmtNJ15X/oJCLCnET9+HCKyhmig+lehZkH9HPfPqG9rvTPKz DknzrLJBef8BoRHFgRp1GilukD/mP0sNqZHO7XfPumh8GH4vPBzypJs6pH7LR5xRciod vHsaLzzopuE/dTeLa58qwjGW0DYNF+QTz7oZakJqXFDHNlB3r2jamIrzP2CXQ1IUzLx3 lc4w== X-Gm-Message-State: ACrzQf3XRzsQ2NUtTfL8AhPOlZdeIsB1c+Gyc6oEcnD85z9OBITyja75 3Yzdpio+6e8snC1g4ITJ5YQqjg== X-Google-Smtp-Source: AMsMyM7R9m1PDf/0y4lVpz2BCJ5SWl4D2p6uX59LgOqpWA1Vco0oGHwT7z6lJdGEs5dJ9TU3VTcxDQ== X-Received: by 2002:a05:600c:19d2:b0:3b4:a4cb:2416 with SMTP id u18-20020a05600c19d200b003b4a4cb2416mr1762608wmq.6.1664267730688; Tue, 27 Sep 2022 01:35:30 -0700 (PDT) Received: from localhost.localdomain (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b003b492b30822sm1122120wmr.2.2022.09.27.01.35.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 01:35:30 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, lee@kernel.org, tony@atomide.com, vigneshr@ti.com, bjorn.andersson@linaro.org, shawnguo@kernel.org, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, marcel.ziswiler@toradex.com, vkoul@kernel.org, biju.das.jz@bp.renesas.com, arnd@arndb.de, jeff@labundy.com Cc: afd@ti.com, khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v5 1/6] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Date: Tue, 27 Sep 2022 10:35:15 +0200 Message-Id: <20220927083520.15766-2-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220927083520.15766-1-jneanne@baylibre.com> References: <20220927083520.15766-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add support fot the TI Power Management IC TPS65219 on the AM642 SKEVM board. Needed for driver testing but official board support pending. TI commitment is required before board upstream kick-off. Signed-off-by: Jerome Neanne Signed-off-by: Markus Schneider-Pargmann --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 104 +++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 2620469a7517..565b50810579 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -150,6 +150,20 @@ vin-supply = <&com8_ls_en>; gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; }; + + vsel_sd_nddr: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel_sd_nddr_pins_default>; + regulator-name = "tps65219-LDO1-SEL-SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; }; &main_pmx0 { @@ -181,6 +195,13 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -267,6 +288,12 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; }; + + vsel_sd_nddr_pins_default: vsel-sd-nddr-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 7) /* (Y7) PRG1_PRU0_GPO0.GPIO0_45 */ + >; + }; }; &mcu_uart0 { @@ -315,6 +342,83 @@ status = "disabled"; }; +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + system-power-controller; + + buck1-supply = <&vcc_3v3_sys>; + buck2-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vcc_3v3_sys>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDSHV_SD_IO_PMIC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDAR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_PHY_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; &main_i2c1 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>;