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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b003b492b30822sm1122120wmr.2.2022.09.27.01.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 01:35:34 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, lee@kernel.org, tony@atomide.com, vigneshr@ti.com, bjorn.andersson@linaro.org, shawnguo@kernel.org, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, marcel.ziswiler@toradex.com, vkoul@kernel.org, biju.das.jz@bp.renesas.com, arnd@arndb.de, jeff@labundy.com Cc: afd@ti.com, khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v5 2/6] DONOTMERGE: arm64: dts: ti: Add pinmux and irq mapping for TPS65219 external interrupts Date: Tue, 27 Sep 2022 10:35:16 +0200 Message-Id: <20220927083520.15766-3-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220927083520.15766-1-jneanne@baylibre.com> References: <20220927083520.15766-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Interrupt occurring on PMIC TPS65219 is propagated to SOC through EXTINTn pin connected to gic500 interrupt controller Needed for driver testing but official board support pending. TI commitment is required before board upstream kick-off. Signed-off-by: Jerome Neanne Signed-off-by: Markus Schneider-Pargmann --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 565b50810579..1f7ce60ecb57 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -294,6 +294,12 @@ AM64X_IOPAD(0x00b8, PIN_INPUT, 7) /* (Y7) PRG1_PRU0_GPO0.GPIO0_45 */ >; }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0278, PIN_INPUT, 0) /* (C19) EXTINTn */ + >; + }; }; &mcu_uart0 { @@ -352,6 +358,10 @@ compatible = "ti,tps65219"; reg = <0x30>; system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; buck1-supply = <&vcc_3v3_sys>; buck2-supply = <&vcc_3v3_sys>;