From patchwork Wed Nov 9 16:09:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Jackson X-Patchwork-Id: 13037665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BDFAC4321E for ; Wed, 9 Nov 2022 16:09:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbiKIQJd (ORCPT ); Wed, 9 Nov 2022 11:09:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231514AbiKIQJV (ORCPT ); Wed, 9 Nov 2022 11:09:21 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55D7F10B7D for ; Wed, 9 Nov 2022 08:09:20 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id ay14-20020a05600c1e0e00b003cf6ab34b61so1575069wmb.2 for ; Wed, 09 Nov 2022 08:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=newflow-co-uk.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eBK4M6em14NDAYl08ahmQwtvd1CwNFvnLrorbySUXHw=; b=eA0Rz0xzZ2vh6exn1saL0VAyz6h/yas7xOMIohoejnFwJeu+S3dVlIhuU5swEWgJbP GegjxhCNDdKzQ631KPcvpWshjjXfF9j6iW7dTTTBLRtMhuRo/FAZN/OZpUyq9ZKgnXGb zGPFtVpEadvXTHKixjUX8H6bYd+7Zod14QbSEgZoGcZyRm6wMwsjz0p7Ym1yegeaMvUR 7iwVXht2WrXK7rqsOmE/C70p5Z+jK7klA2U3CfluvDzM79FkGyjCibZiZvhYzo2nfPJv kne7wvvog4vxCAebsjf39a2jBjEITSMfsjU36sXf+82nbkI7JUn5hrHqCaJkft89+uHd ocEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eBK4M6em14NDAYl08ahmQwtvd1CwNFvnLrorbySUXHw=; b=Vb5TPA9W9/At5Klwdo38KKBfP0AsWhEbzLfG1PcyQiOkQKZusEQAMlZuEgRcbRM85S 5D4tnn2yDfrOCoWIrROuOix+JiqzINYMCqbVHd50Do7qpxhhPK4BPLGcCcYQhNZb71Kp IVf8Th0R42rAVJng/duNW5yC76hQkMfNVdbIkFH0ZR+WEomn/tT+WD/D2V7JGzjpj9qU rFk7VZD2F1Bqo+qHVmPTYfhhkt9ApiqQujQKoKe2supe3/N+uxy3sOQlITS2wARfWC/V mIn0JfQy30Iho62O9VW7Nkcp0ks9dtlz9ozhIFQpH1FsgyNDDsLX0ZhVlTj6MP98ONHE eXJg== X-Gm-Message-State: ACrzQf0lFIeo/7cvDROiw5KqlBw2IgZhOEf18s/0R5GbpkqqJ/YVD4pM Js/33AV5bxnHMxYgQ9XlLEaRrQ== X-Google-Smtp-Source: AMsMyM6OPBpiNB6dnNVcoer8YRbGpHNjQBls4eJivGZjIFwLNbkdGzxnM31KXy6Fyy2zGtVso18cvQ== X-Received: by 2002:a05:600c:448a:b0:3cf:a359:9f4d with SMTP id e10-20020a05600c448a00b003cfa3599f4dmr14719246wmo.133.1668010158775; Wed, 09 Nov 2022 08:09:18 -0800 (PST) Received: from mpfj-unity.. ([94.12.112.226]) by smtp.gmail.com with ESMTPSA id n4-20020a5d6604000000b002366fb99cdasm13307772wru.50.2022.11.09.08.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 08:09:18 -0800 (PST) From: Mark Jackson To: Mark Jackson , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Krzysztof Kozlowski , linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] ARM: dts: nanobone: Fix GPIO settings for RTS/CTS pins on UART3 & 4 Date: Wed, 9 Nov 2022 16:09:00 +0000 Message-Id: <20221109160904.183147-2-mpfj@newflow.co.uk> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221109160904.183147-1-mpfj@newflow.co.uk> References: <20221109160904.183147-1-mpfj@newflow.co.uk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The NanoBone platform uses GPIO pins for RTS/CTS control. The DTS still uses the hardware RTS/CTS pins so this needs fixing. Signed-off-by: Mark Jackson --- arch/arm/boot/dts/am335x-nano.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index b6f2567bd65a..05cbfe24f778 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -120,8 +120,8 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd uart3_pins: uart3_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; @@ -129,8 +129,8 @@ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in uart4_pins: uart4_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ >;