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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id h3-20020a5ecb43000000b0079fdeed3ab6sm56895iok.40.2023.10.04.17.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 17:04:08 -0700 (PDT) From: Adam Ford To: linux-omap@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , =?utf-8?q?Beno?= =?utf-8?q?=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Derald D. Woods" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/2] arm: dts: am3517-evm: Enable Ethernet PHY Interrupt Date: Wed, 4 Oct 2023 19:04:02 -0500 Message-Id: <20231005000402.50879-2-aford173@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231005000402.50879-1-aford173@gmail.com> References: <20231005000402.50879-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The Ethernet PHY interrupt pin is routed to GPIO_58. Create a PHY node to configure this GPIO for the interrupt to avoid polling. Signed-off-by: Adam Ford --- V3: Fix issue where V2 wasn't properly properly commit-ammended, so V2 patch didn't properly generate V2: Attempted (but failed) to fix ethernet-phy-pins naming diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts index 866f68c5b504..40f15da81043 100644 --- a/arch/arm/boot/dts/ti/omap/am3517-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts @@ -172,11 +172,24 @@ hsusb1_phy: hsusb1_phy { &davinci_emac { pinctrl-names = "default"; pinctrl-0 = <ðernet_pins>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; status = "okay"; }; &davinci_mdio { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + ethphy0: ethernet-phy@0 { + pinctrl-names = "default"; + pinctrl-0 = <&enet_phy_pins>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; /* gpio_58 */ + }; }; &dss { @@ -257,6 +270,12 @@ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ >; }; + enet_phy_pins: ethernet-phy-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20bc, PIN_INPUT | MUX_MODE4) /* gpmc_ncs7.gpio_57 */ + >; + }; + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */