@@ -351,7 +351,7 @@ void pci_bus_add_device(struct pci_dev *dev)
dev->match_driver = !dn || of_device_is_available(dn);
retval = device_attach(&dev->dev);
if (retval < 0 && retval != -EPROBE_DEFER)
- pci_warn(dev, "device attach failed (%d)\n", retval);
+ pci_warn(dev, "device attach failed: %pe\n", ERR_PTR(retval));
pci_dev_assign_added(dev, true);
}
@@ -801,7 +801,7 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
if (IS_ERR(reset)) {
ret = PTR_ERR(reset);
- dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
+ dev_err(&pdev->dev, "gpio request failed: %pe\n", ERR_PTR(ret));
goto err_gpio;
}
@@ -183,7 +183,7 @@ static inline struct clk *meson_pcie_probe_clock(struct device *dev,
if (rate) {
ret = clk_set_rate(clk, rate);
if (ret) {
- dev_err(dev, "set clk rate failed, ret = %d\n", ret);
+ dev_err(dev, "set clk rate failed: %pe\n", ERR_PTR(ret));
return ERR_PTR(ret);
}
}
@@ -416,7 +416,7 @@ static int meson_pcie_probe(struct platform_device *pdev)
mp->phy = devm_phy_get(dev, "pcie");
if (IS_ERR(mp->phy)) {
- dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
+ dev_err(dev, "get phy failed: %pe\n", mp->phy);
return PTR_ERR(mp->phy);
}
@@ -428,31 +428,31 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = meson_pcie_get_resets(mp);
if (ret) {
- dev_err(dev, "get reset resource failed, %d\n", ret);
+ dev_err(dev, "get reset resource failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_get_mems(pdev, mp);
if (ret) {
- dev_err(dev, "get memory resource failed, %d\n", ret);
+ dev_err(dev, "get memory resource failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_power_on(mp);
if (ret) {
- dev_err(dev, "phy power on failed, %d\n", ret);
+ dev_err(dev, "phy power on failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_reset(mp);
if (ret) {
- dev_err(dev, "reset failed, %d\n", ret);
+ dev_err(dev, "reset failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
ret = meson_pcie_probe_clocks(mp);
if (ret) {
- dev_err(dev, "init clock resources failed, %d\n", ret);
+ dev_err(dev, "init clock resources failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
@@ -460,7 +460,7 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = dw_pcie_host_init(&pci->pp);
if (ret < 0) {
- dev_err(dev, "Add PCIe port failed, %d\n", ret);
+ dev_err(dev, "Add PCIe port failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
@@ -134,7 +134,7 @@ static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie)
ret = armada8k_pcie_enable_phys(pcie);
if (ret)
- dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret);
+ dev_err(dev, "Failed to initialize PHY(s): %pe\n", ERR_PTR(ret));
return ret;
}
@@ -251,7 +251,7 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
ret = dw_pcie_host_init(pp);
if (ret) {
- dev_err(dev, "failed to initialize host: %d\n", ret);
+ dev_err(dev, "failed to initialize host: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -230,7 +230,7 @@ static int histb_pcie_host_enable(struct dw_pcie_rp *pp)
if (hipcie->vpcie) {
ret = regulator_enable(hipcie->vpcie);
if (ret) {
- dev_err(dev, "failed to enable regulator: %d\n", ret);
+ dev_err(dev, "failed to enable regulator: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -337,14 +337,14 @@ static int histb_pcie_probe(struct platform_device *pdev)
GPIOD_OUT_HIGH);
ret = PTR_ERR_OR_ZERO(hipcie->reset_gpio);
if (ret) {
- dev_err(dev, "unable to request reset gpio: %d\n", ret);
+ dev_err(dev, "unable to request reset gpio: %pe\n", ERR_PTR(ret));
return ret;
}
ret = gpiod_set_consumer_name(hipcie->reset_gpio,
"PCIe device power control");
if (ret) {
- dev_err(dev, "unable to set reset gpio name: %d\n", ret);
+ dev_err(dev, "unable to set reset gpio name: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -155,7 +155,7 @@ static int intel_pcie_ep_rst_init(struct intel_pcie *pcie)
if (IS_ERR(pcie->reset_gpio)) {
ret = PTR_ERR(pcie->reset_gpio);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret);
+ dev_err(dev, "Failed to request PCIe GPIO: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -214,7 +214,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->core_clk)) {
ret = PTR_ERR(pcie->core_clk);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get clks: %d\n", ret);
+ dev_err(dev, "Failed to get clks: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -222,7 +222,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->core_rst)) {
ret = PTR_ERR(pcie->core_rst);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get resets: %d\n", ret);
+ dev_err(dev, "Failed to get resets: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -239,7 +239,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->phy)) {
ret = PTR_ERR(pcie->phy);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);
+ dev_err(dev, "Couldn't get pcie-phy: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -295,7 +295,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
+ dev_err(pcie->pci.dev, "Core clock enable failed: %pe\n", ERR_PTR(ret));
goto clk_err;
}
@@ -377,7 +377,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
ret = dw_pcie_host_init(pp);
if (ret) {
keembay_ep_reset_assert(pcie);
- dev_err(dev, "Failed to initialize host: %d\n", ret);
+ dev_err(dev, "Failed to initialize host: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -421,7 +421,7 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
ret = of_pci_get_devfn(child);
if (ret < 0) {
- dev_err(dev, "failed to parse devfn: %d\n", ret);
+ dev_err(dev, "failed to parse devfn: %pe\n", ERR_PTR(ret));
goto put_node;
}
@@ -555,8 +555,8 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
for (i = 0; i < kirin_pcie->num_slots; i++) {
ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
if (ret) {
- dev_err(pci->dev, "PERST# %s error: %d\n",
- kirin_pcie->reset_names[i], ret);
+ dev_err(pci->dev, "PERST# %s error: %pe\n",
+ kirin_pcie->reset_names[i], ERR_PTR(ret));
}
}
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
@@ -296,8 +296,8 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
if (ret)
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
}
static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
@@ -334,8 +334,8 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
*/
ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
goto err_phy_off;
}
@@ -368,7 +368,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
ret = qcom_pcie_enable_resources(pcie_ep);
if (ret) {
- dev_err(dev, "Failed to enable resources: %d\n", ret);
+ dev_err(dev, "Failed to enable resources: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -465,7 +465,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
if (ret) {
- dev_err(dev, "Failed to complete initialization: %d\n", ret);
+ dev_err(dev, "Failed to complete initialization: %pe\n", ERR_PTR(ret));
goto err_disable_resources;
}
@@ -591,7 +591,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
if (ret) {
- dev_err(dev, "Failed to get io resources %d\n", ret);
+ dev_err(dev, "Failed to get io resources: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -824,13 +824,13 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
ret = qcom_pcie_enable_resources(pcie_ep);
if (ret) {
- dev_err(dev, "Failed to enable resources: %d\n", ret);
+ dev_err(dev, "Failed to enable resources: %pe\n", ERR_PTR(ret));
return ret;
}
ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
if (ret) {
- dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
+ dev_err(dev, "Failed to initialize endpoint: %pe\n", ERR_PTR(ret));
goto err_disable_resources;
}
@@ -931,7 +931,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
ret = reset_control_assert(res->rst);
if (ret) {
- dev_err(dev, "reset assert failed (%d)\n", ret);
+ dev_err(dev, "reset assert failed: %pe\n", ERR_PTR(ret));
goto err_disable_clocks;
}
@@ -939,7 +939,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->rst);
if (ret) {
- dev_err(dev, "reset deassert failed (%d)\n", ret);
+ dev_err(dev, "reset deassert failed: %pe\n", ERR_PTR(ret));
goto err_disable_clocks;
}
@@ -1135,7 +1135,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
ret = reset_control_assert(res->rst);
if (ret) {
- dev_err(dev, "reset assert failed (%d)\n", ret);
+ dev_err(dev, "reset assert failed: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1147,7 +1147,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->rst);
if (ret) {
- dev_err(dev, "reset deassert failed (%d)\n", ret);
+ dev_err(dev, "reset deassert failed: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1418,8 +1418,8 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
*/
ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
return ret;
}
@@ -1448,8 +1448,8 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
}
}
@@ -1610,7 +1610,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
*/
ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
if (ret) {
- dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret);
+ dev_err(dev, "Failed to set interconnect bandwidth: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1114,38 +1114,38 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
if (ret < 0) {
- dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
+ dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
&pcie->aspm_pwr_on_t);
if (ret < 0)
- dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
- ret);
+ dev_info(pcie->dev, "Failed to read ASPM Power On time: %pe\n",
+ ERR_PTR(ret));
ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
&pcie->aspm_l0s_enter_lat);
if (ret < 0)
dev_info(pcie->dev,
- "Failed to read ASPM L0s Entrance latency: %d\n", ret);
+ "Failed to read ASPM L0s Entrance latency: %pe\n", ERR_PTR(ret));
ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
+ dev_err(pcie->dev, "Failed to read num-lanes: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
if (ret) {
- dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
+ dev_err(pcie->dev, "Failed to read Controller-ID: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_count_strings(np, "phy-names");
if (ret < 0) {
- dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to find PHY entries: %pe\n",
+ ERR_PTR(ret));
return ret;
}
pcie->phy_count = ret;
@@ -1186,8 +1186,8 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
level = KERN_DEBUG;
dev_printk(level, pcie->dev,
- dev_fmt("Failed to get PERST GPIO: %d\n"),
- err);
+ dev_fmt("Failed to get PERST GPIO: %pe\n"),
+ ERR_PTR(err));
return err;
}
@@ -1202,8 +1202,8 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
level = KERN_DEBUG;
dev_printk(level, pcie->dev,
- dev_fmt("Failed to get REFCLK select GPIOs: %d\n"),
- err);
+ dev_fmt("Failed to get REFCLK select GPIOs: %pe\n"),
+ ERR_PTR(err));
pcie->pex_refclk_sel_gpiod = NULL;
}
@@ -1336,7 +1336,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
ret = regulator_enable(pcie->slot_ctl_3v3);
if (ret < 0) {
dev_err(pcie->dev,
- "Failed to enable 3.3V slot supply: %d\n", ret);
+ "Failed to enable 3.3V slot supply: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -1345,7 +1345,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
ret = regulator_enable(pcie->slot_ctl_12v);
if (ret < 0) {
dev_err(pcie->dev,
- "Failed to enable 12V slot supply: %d\n", ret);
+ "Failed to enable 12V slot supply: %pe\n", ERR_PTR(ret));
goto fail_12v_enable;
}
}
@@ -1383,14 +1383,14 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
dev_err(pcie->dev,
- "Failed to enable controller %u: %d\n", pcie->cid, ret);
+ "Failed to enable controller %u: %pe\n", pcie->cid, ERR_PTR(ret));
return ret;
}
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
if (ret) {
- dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to init UPHY: %pe\n", ERR_PTR(ret));
goto fail_pll_init;
}
}
@@ -1401,20 +1401,20 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = regulator_enable(pcie->pex_ctl_supply);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable regulator: %pe\n", ERR_PTR(ret));
goto fail_reg_en;
}
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable core clock: %pe\n", ERR_PTR(ret));
goto fail_core_clk;
}
ret = reset_control_deassert(pcie->core_apb_rst);
if (ret) {
- dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to deassert core APB reset: %pe\n",
+ ERR_PTR(ret));
goto fail_core_apb_rst;
}
@@ -1431,7 +1431,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = tegra_pcie_enable_phy(pcie);
if (ret) {
- dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable PHY: %pe\n", ERR_PTR(ret));
goto fail_phy;
}
@@ -1503,32 +1503,32 @@ static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
ret = reset_control_assert(pcie->core_rst);
if (ret)
- dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret);
+ dev_err(pcie->dev, "Failed to assert \"core\" reset: %pe\n", ERR_PTR(ret));
tegra_pcie_disable_phy(pcie);
ret = reset_control_assert(pcie->core_apb_rst);
if (ret)
- dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
+ dev_err(pcie->dev, "Failed to assert APB reset: %pe\n", ERR_PTR(ret));
clk_disable_unprepare(pcie->core_clk);
ret = regulator_disable(pcie->pex_ctl_supply);
if (ret)
- dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
+ dev_err(pcie->dev, "Failed to disable regulator: %pe\n", ERR_PTR(ret));
tegra_pcie_disable_slot_regulators(pcie);
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to deinit UPHY: %pe\n", ERR_PTR(ret));
}
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
- pcie->cid, ret);
+ dev_err(pcie->dev, "Failed to disable controller %d: %pe\n",
+ pcie->cid, ERR_PTR(ret));
}
static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
@@ -1545,7 +1545,7 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
ret = dw_pcie_host_init(pp);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
+ dev_err(pcie->dev, "Failed to add PCIe port: %pe\n", ERR_PTR(ret));
goto fail_host_init;
}
@@ -1652,20 +1652,20 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
- dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
- ret);
+ dev_err(dev, "Failed to get runtime sync for PCIe dev: %pe\n",
+ ERR_PTR(ret));
goto fail_pm_get_sync;
}
ret = pinctrl_pm_select_default_state(dev);
if (ret < 0) {
- dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
+ dev_err(dev, "Failed to configure sideband pins: %pe\n", ERR_PTR(ret));
goto fail_pm_get_sync;
}
ret = tegra_pcie_init_controller(pcie);
if (ret < 0) {
- dev_err(dev, "Failed to initialize controller: %d\n", ret);
+ dev_err(dev, "Failed to initialize controller: %pe\n", ERR_PTR(ret));
goto fail_pm_get_sync;
}
@@ -1713,7 +1713,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
LTSSM_STATE_PRE_DETECT,
1, LTSSM_TIMEOUT);
if (ret)
- dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
+ dev_err(pcie->dev, "Failed to go Detect state: %pe\n", ERR_PTR(ret));
dw_pcie_ep_cleanup(&pcie->pci.ep);
@@ -1730,13 +1730,13 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to turn off UPHY: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to turn off UPHY: %pe\n",
+ ERR_PTR(ret));
}
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to turn off UPHY: %pe\n", ERR_PTR(ret));
pcie->ep_state = EP_STATE_DISABLED;
dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
@@ -1756,42 +1756,42 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
- dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
- ret);
+ dev_err(dev, "Failed to get runtime sync for PCIe dev: %pe\n",
+ ERR_PTR(ret));
return;
}
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
- dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
- pcie->cid, ret);
+ dev_err(pcie->dev, "Failed to enable controller %u: %pe\n",
+ pcie->cid, ERR_PTR(ret));
goto fail_set_ctrl_state;
}
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
if (ret) {
- dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n",
- ret);
+ dev_err(dev, "Failed to init UPHY for PCIe EP: %pe\n",
+ ERR_PTR(ret));
goto fail_pll_init;
}
}
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(dev, "Failed to enable core clock: %d\n", ret);
+ dev_err(dev, "Failed to enable core clock: %pe\n", ERR_PTR(ret));
goto fail_core_clk_enable;
}
ret = reset_control_deassert(pcie->core_apb_rst);
if (ret) {
- dev_err(dev, "Failed to deassert core APB reset: %d\n", ret);
+ dev_err(dev, "Failed to deassert core APB reset: %pe\n", ERR_PTR(ret));
goto fail_core_apb_rst;
}
ret = tegra_pcie_enable_phy(pcie);
if (ret) {
- dev_err(dev, "Failed to enable PHY: %d\n", ret);
+ dev_err(dev, "Failed to enable PHY: %pe\n", ERR_PTR(ret));
goto fail_phy;
}
@@ -1899,7 +1899,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
ret = dw_pcie_ep_init_registers(ep);
if (ret) {
- dev_err(dev, "Failed to complete initialization: %d\n", ret);
+ dev_err(dev, "Failed to complete initialization: %pe\n", ERR_PTR(ret));
goto fail_init_complete;
}
@@ -2044,14 +2044,14 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
if (ret < 0) {
- dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n",
- ret);
+ dev_err(dev, "Failed to set PERST GPIO debounce time: %pe\n",
+ ERR_PTR(ret));
return ret;
}
ret = gpiod_to_irq(pcie->pex_rst_gpiod);
if (ret < 0) {
- dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret);
+ dev_err(dev, "Failed to get IRQ for PERST GPIO: %pe\n", ERR_PTR(ret));
return ret;
}
pcie->pex_rst_irq = (unsigned int)ret;
@@ -2073,7 +2073,7 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
name, (void *)pcie);
if (ret < 0) {
- dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
+ dev_err(dev, "Failed to request IRQ for PERST: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -2081,8 +2081,8 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
ret = dw_pcie_ep_init(ep);
if (ret) {
- dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n",
- ret);
+ dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %pe\n",
+ ERR_PTR(ret));
pm_runtime_disable(dev);
return ret;
}
@@ -2152,15 +2152,15 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
if (IS_ERR(pcie->pex_ctl_supply)) {
ret = PTR_ERR(pcie->pex_ctl_supply);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get regulator: %ld\n",
- PTR_ERR(pcie->pex_ctl_supply));
+ dev_err(dev, "Failed to get regulator: %pe\n",
+ pcie->pex_ctl_supply);
return ret;
}
pcie->core_clk = devm_clk_get(dev, "core");
if (IS_ERR(pcie->core_clk)) {
- dev_err(dev, "Failed to get core clock: %ld\n",
- PTR_ERR(pcie->core_clk));
+ dev_err(dev, "Failed to get core clock: %pe\n",
+ pcie->core_clk);
return PTR_ERR(pcie->core_clk);
}
@@ -2177,8 +2177,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
if (IS_ERR(pcie->core_apb_rst)) {
- dev_err(dev, "Failed to get APB reset: %ld\n",
- PTR_ERR(pcie->core_apb_rst));
+ dev_err(dev, "Failed to get APB reset: %pe\n",
+ pcie->core_apb_rst);
return PTR_ERR(pcie->core_apb_rst);
}
@@ -2197,7 +2197,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
if (IS_ERR(phys[i])) {
ret = PTR_ERR(phys[i]);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get PHY: %d\n", ret);
+ dev_err(dev, "Failed to get PHY: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -2219,8 +2219,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pcie->core_rst = devm_reset_control_get(dev, "core");
if (IS_ERR(pcie->core_rst)) {
- dev_err(dev, "Failed to get core reset: %ld\n",
- PTR_ERR(pcie->core_rst));
+ dev_err(dev, "Failed to get core reset: %pe\n",
+ pcie->core_rst);
return PTR_ERR(pcie->core_rst);
}
@@ -2247,8 +2247,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
IRQF_SHARED, "tegra-pcie-intr", pcie);
if (ret) {
- dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
- ret);
+ dev_err(dev, "Failed to request IRQ %d: %pe\n", pp->irq,
+ ERR_PTR(ret));
goto fail;
}
@@ -2266,8 +2266,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
IRQF_SHARED | IRQF_ONESHOT,
"tegra-pcie-ep-intr", pcie);
if (ret) {
- dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
- ret);
+ dev_err(dev, "Failed to request IRQ %d: %pe\n", pp->irq,
+ ERR_PTR(ret));
goto fail;
}
@@ -2364,7 +2364,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
if (ret < 0) {
- dev_err(dev, "Failed to init host: %d\n", ret);
+ dev_err(dev, "Failed to init host: %pe\n", ERR_PTR(ret));
goto fail_host_init;
}
@@ -388,7 +388,7 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
priv->phy = devm_phy_optional_get(dev, "pcie-phy");
if (IS_ERR(priv->phy)) {
ret = PTR_ERR(priv->phy);
- dev_err(dev, "Failed to get phy (%d)\n", ret);
+ dev_err(dev, "Failed to get phy: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1743,14 +1743,14 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie)
/* Old bindings miss the PHY handle */
if (IS_ERR(pcie->phy)) {
- dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
+ dev_warn(dev, "PHY unavailable: %pe\n", pcie->phy);
pcie->phy = NULL;
return 0;
}
ret = advk_pcie_enable_phy(pcie);
if (ret)
- dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
+ dev_err(dev, "Failed to initialize PHY: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1863,7 +1863,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
if (ret) {
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get reset-gpio: %i\n", ret);
+ dev_err(dev, "Failed to get reset-gpio: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -502,7 +502,7 @@ static int faraday_pci_probe(struct platform_device *pdev)
ret = pci_scan_root_bus_bridge(host);
if (ret) {
- dev_err(dev, "failed to scan host: %d\n", ret);
+ dev_err(dev, "failed to scan host: %pe\n", ERR_PTR(ret));
return ret;
}
p->bus = host->bus;
@@ -946,7 +946,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
/* wait for the PLL to lock */
err = tegra_pcie_pll_wait(pcie, 500);
if (err < 0) {
- dev_err(dev, "PLL failed to lock: %d\n", err);
+ dev_err(dev, "PLL failed to lock: %pe\n", ERR_PTR(err));
return err;
}
@@ -997,7 +997,7 @@ static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
err = phy_power_on(port->phys[i]);
if (err < 0) {
- dev_err(dev, "failed to power on PHY#%u: %d\n", i, err);
+ dev_err(dev, "failed to power on PHY#%u: %pe\n", i, ERR_PTR(err));
return err;
}
}
@@ -1014,8 +1014,8 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
err = phy_power_off(port->phys[i]);
if (err < 0) {
- dev_err(dev, "failed to power off PHY#%u: %d\n", i,
- err);
+ dev_err(dev, "failed to power off PHY#%u: %pe\n", i,
+ ERR_PTR(err));
return err;
}
}
@@ -1036,7 +1036,7 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
err = tegra_pcie_phy_enable(pcie);
if (err < 0)
- dev_err(dev, "failed to power on PHY: %d\n", err);
+ dev_err(dev, "failed to power on PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1045,8 +1045,8 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
err = tegra_pcie_port_phy_power_on(port);
if (err < 0) {
dev_err(dev,
- "failed to power on PCIe port %u PHY: %d\n",
- port->index, err);
+ "failed to power on PCIe port %u PHY: %pe\n",
+ port->index, ERR_PTR(err));
return err;
}
}
@@ -1067,7 +1067,7 @@ static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
err = tegra_pcie_phy_disable(pcie);
if (err < 0)
- dev_err(dev, "failed to power off PHY: %d\n", err);
+ dev_err(dev, "failed to power off PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1076,8 +1076,8 @@ static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
err = tegra_pcie_port_phy_power_off(port);
if (err < 0) {
dev_err(dev,
- "failed to power off PCIe port %u PHY: %d\n",
- port->index, err);
+ "failed to power off PCIe port %u PHY: %pe\n",
+ port->index, ERR_PTR(err));
return err;
}
}
@@ -1167,7 +1167,7 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
if (err < 0)
- dev_warn(dev, "failed to disable regulators: %d\n", err);
+ dev_warn(dev, "failed to disable regulators: %pe\n", ERR_PTR(err));
}
static int tegra_pcie_power_on(struct tegra_pcie *pcie)
@@ -1186,38 +1186,38 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
/* enable regulators */
err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
if (err < 0)
- dev_err(dev, "failed to enable regulators: %d\n", err);
+ dev_err(dev, "failed to enable regulators: %pe\n", ERR_PTR(err));
if (!dev->pm_domain) {
err = tegra_powergate_power_on(TEGRA_POWERGATE_PCIE);
if (err) {
- dev_err(dev, "failed to power ungate: %d\n", err);
+ dev_err(dev, "failed to power ungate: %pe\n", ERR_PTR(err));
goto regulator_disable;
}
err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_PCIE);
if (err) {
- dev_err(dev, "failed to remove clamp: %d\n", err);
+ dev_err(dev, "failed to remove clamp: %pe\n", ERR_PTR(err));
goto powergate;
}
}
err = clk_prepare_enable(pcie->afi_clk);
if (err < 0) {
- dev_err(dev, "failed to enable AFI clock: %d\n", err);
+ dev_err(dev, "failed to enable AFI clock: %pe\n", ERR_PTR(err));
goto powergate;
}
if (soc->has_cml_clk) {
err = clk_prepare_enable(pcie->cml_clk);
if (err < 0) {
- dev_err(dev, "failed to enable CML clock: %d\n", err);
+ dev_err(dev, "failed to enable CML clock: %pe\n", ERR_PTR(err));
goto disable_afi_clk;
}
}
err = clk_prepare_enable(pcie->pll_e);
if (err < 0) {
- dev_err(dev, "failed to enable PLLE clock: %d\n", err);
+ dev_err(dev, "failed to enable PLLE clock: %pe\n", ERR_PTR(err));
goto disable_cml_clk;
}
@@ -1303,13 +1303,13 @@ static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
pcie->phy = devm_phy_optional_get(dev, "pcie");
if (IS_ERR(pcie->phy)) {
err = PTR_ERR(pcie->phy);
- dev_err(dev, "failed to get PHY: %d\n", err);
+ dev_err(dev, "failed to get PHY: %pe\n", ERR_PTR(err));
return err;
}
err = phy_init(pcie->phy);
if (err < 0) {
- dev_err(dev, "failed to initialize PHY: %d\n", err);
+ dev_err(dev, "failed to initialize PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1350,15 +1350,15 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
if (IS_ERR(phy)) {
- dev_err(dev, "failed to get PHY#%u: %ld\n", i,
- PTR_ERR(phy));
+ dev_err(dev, "failed to get PHY#%u: %pe\n", i,
+ phy);
return PTR_ERR(phy);
}
err = phy_init(phy);
if (err < 0) {
- dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
- err);
+ dev_err(dev, "failed to initialize PHY#%u: %pe\n", i,
+ ERR_PTR(err));
return err;
}
@@ -1396,7 +1396,7 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
if (pcie->legacy_phy) {
err = phy_exit(pcie->phy);
if (err < 0)
- dev_err(dev, "failed to teardown PHY: %d\n", err);
+ dev_err(dev, "failed to teardown PHY: %pe\n", ERR_PTR(err));
return;
}
@@ -1404,8 +1404,8 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
for (i = 0; i < port->lanes; i++) {
err = phy_exit(port->phys[i]);
if (err < 0)
- dev_err(dev, "failed to teardown PHY#%u: %d\n",
- i, err);
+ dev_err(dev, "failed to teardown PHY#%u: %pe\n",
+ i, ERR_PTR(err));
}
}
}
@@ -1420,20 +1420,20 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = tegra_pcie_clocks_get(pcie);
if (err) {
- dev_err(dev, "failed to get clocks: %d\n", err);
+ dev_err(dev, "failed to get clocks: %pe\n", ERR_PTR(err));
return err;
}
err = tegra_pcie_resets_get(pcie);
if (err) {
- dev_err(dev, "failed to get resets: %d\n", err);
+ dev_err(dev, "failed to get resets: %pe\n", ERR_PTR(err));
return err;
}
if (soc->program_uphy) {
err = tegra_pcie_phys_get(pcie);
if (err < 0) {
- dev_err(dev, "failed to get PHYs: %d\n", err);
+ dev_err(dev, "failed to get PHYs: %pe\n", ERR_PTR(err));
return err;
}
}
@@ -1477,7 +1477,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
if (err) {
- dev_err(dev, "failed to register IRQ: %d\n", err);
+ dev_err(dev, "failed to register IRQ: %pe\n", ERR_PTR(err));
goto phys_put;
}
@@ -2127,7 +2127,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_pci_get_devfn(port);
if (err < 0) {
- dev_err(dev, "failed to parse address: %d\n", err);
+ dev_err(dev, "failed to parse address: %pe\n", ERR_PTR(err));
goto err_node_put;
}
@@ -2143,8 +2143,8 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_property_read_u32(port, "nvidia,num-lanes", &value);
if (err < 0) {
- dev_err(dev, "failed to parse # of lanes: %d\n",
- err);
+ dev_err(dev, "failed to parse # of lanes: %pe\n",
+ ERR_PTR(err));
goto err_node_put;
}
@@ -2172,7 +2172,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_address_to_resource(port, 0, &rp->regs);
if (err < 0) {
- dev_err(dev, "failed to parse address: %d\n", err);
+ dev_err(dev, "failed to parse address: %pe\n", ERR_PTR(err));
goto err_node_put;
}
@@ -2640,20 +2640,20 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = tegra_pcie_get_resources(pcie);
if (err < 0) {
- dev_err(dev, "failed to request resources: %d\n", err);
+ dev_err(dev, "failed to request resources: %pe\n", ERR_PTR(err));
return err;
}
err = tegra_pcie_msi_setup(pcie);
if (err < 0) {
- dev_err(dev, "failed to enable MSI support: %d\n", err);
+ dev_err(dev, "failed to enable MSI support: %pe\n", ERR_PTR(err));
goto put_resources;
}
pm_runtime_enable(pcie->dev);
err = pm_runtime_get_sync(pcie->dev);
if (err < 0) {
- dev_err(dev, "fail to enable pcie controller: %d\n", err);
+ dev_err(dev, "fail to enable pcie controller: %pe\n", ERR_PTR(err));
goto pm_runtime_put;
}
@@ -2662,7 +2662,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = pci_host_probe(host);
if (err < 0) {
- dev_err(dev, "failed to register host: %d\n", err);
+ dev_err(dev, "failed to register host: %pe\n", ERR_PTR(err));
goto pm_runtime_put;
}
@@ -2723,7 +2723,7 @@ static int tegra_pcie_pm_suspend(struct device *dev)
if (pcie->soc->program_uphy) {
err = tegra_pcie_phy_power_off(pcie);
if (err < 0)
- dev_err(dev, "failed to power off PHY(s): %d\n", err);
+ dev_err(dev, "failed to power off PHY(s): %pe\n", ERR_PTR(err));
}
reset_control_assert(pcie->pex_rst);
@@ -2745,13 +2745,13 @@ static int tegra_pcie_pm_resume(struct device *dev)
err = tegra_pcie_power_on(pcie);
if (err) {
- dev_err(dev, "tegra pcie power on fail: %d\n", err);
+ dev_err(dev, "tegra pcie power on fail: %pe\n", ERR_PTR(err));
return err;
}
err = pinctrl_pm_select_default_state(dev);
if (err < 0) {
- dev_err(dev, "failed to disable PCIe IO DPD: %d\n", err);
+ dev_err(dev, "failed to disable PCIe IO DPD: %pe\n", ERR_PTR(err));
goto poweroff;
}
@@ -2763,7 +2763,7 @@ static int tegra_pcie_pm_resume(struct device *dev)
err = clk_prepare_enable(pcie->pex_clk);
if (err) {
- dev_err(dev, "failed to enable PEX clock: %d\n", err);
+ dev_err(dev, "failed to enable PEX clock: %pe\n", ERR_PTR(err));
goto pex_dpd_enable;
}
@@ -2772,7 +2772,7 @@ static int tegra_pcie_pm_resume(struct device *dev)
if (pcie->soc->program_uphy) {
err = tegra_pcie_phy_power_on(pcie);
if (err < 0) {
- dev_err(dev, "failed to power on PHY(s): %d\n", err);
+ dev_err(dev, "failed to power on PHY(s): %pe\n", ERR_PTR(err));
goto disable_pex_clk;
}
}
@@ -206,8 +206,8 @@ static int xgene_get_csr_resource(struct acpi_device *adev,
acpi_dev_filter_resource_type_cb,
(void *) flags);
if (ret < 0) {
- dev_err(dev, "failed to parse _CRS method, error code %d\n",
- ret);
+ dev_err(dev, "failed to parse _CRS method, error code %pe\n",
+ ERR_PTR(ret));
return ret;
}
@@ -1175,7 +1175,7 @@ static int mc_host_probe(struct platform_device *pdev)
ret = mc_pcie_init_clks(dev);
if (ret) {
- dev_err(dev, "failed to get clock resources, error %d\n", ret);
+ dev_err(dev, "failed to get clock resources, error: %pe\n", ERR_PTR(ret));
return -ENODEV;
}
@@ -78,7 +78,7 @@ static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
writel(L1IATN, pcie_base + PMCTLR);
ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
val & L1FAEG, 10, 1000);
- WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
+ WARN(ret, "Timeout waiting for L1 link state, ret=%pe\n", ERR_PTR(ret));
writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
}
@@ -782,7 +782,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
IRQF_SHARED | IRQF_NO_THREAD,
rcar_msi_bottom_chip.name, host);
if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
+ dev_err(dev, "failed to request IRQ: %pe\n", ERR_PTR(err));
goto err;
}
@@ -790,7 +790,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
IRQF_SHARED | IRQF_NO_THREAD,
rcar_msi_bottom_chip.name, host);
if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
+ dev_err(dev, "failed to request IRQ: %pe\n", ERR_PTR(err));
goto err;
}
@@ -996,13 +996,13 @@ static int rcar_pcie_probe(struct platform_device *pdev)
err = rcar_pcie_get_resources(host);
if (err < 0) {
- dev_err(dev, "failed to request resources: %d\n", err);
+ dev_err(dev, "failed to request resources: %pe\n", ERR_PTR(err));
goto err_pm_put;
}
err = clk_prepare_enable(host->bus_clk);
if (err) {
- dev_err(dev, "failed to enable bus clock: %d\n", err);
+ dev_err(dev, "failed to enable bus clock: %pe\n", ERR_PTR(err));
goto err_unmap_msi_irqs;
}
@@ -1031,8 +1031,8 @@ static int rcar_pcie_probe(struct platform_device *pdev)
err = rcar_pcie_enable_msi(host);
if (err < 0) {
dev_err(dev,
- "failed to enable MSI support: %d\n",
- err);
+ "failed to enable MSI support: %pe\n",
+ ERR_PTR(err));
goto err_phy_shutdown;
}
}
@@ -169,51 +169,51 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_assert(rockchip->aclk_rst);
if (err) {
- dev_err(dev, "assert aclk_rst err %d\n", err);
+ dev_err(dev, "assert aclk_rst err: %pe\n", ERR_PTR(err));
return err;
}
err = reset_control_assert(rockchip->pclk_rst);
if (err) {
- dev_err(dev, "assert pclk_rst err %d\n", err);
+ dev_err(dev, "assert pclk_rst err: %pe\n", ERR_PTR(err));
return err;
}
err = reset_control_assert(rockchip->pm_rst);
if (err) {
- dev_err(dev, "assert pm_rst err %d\n", err);
+ dev_err(dev, "assert pm_rst err: %pe\n", ERR_PTR(err));
return err;
}
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_init(rockchip->phys[i]);
if (err) {
- dev_err(dev, "init phy%d err %d\n", i, err);
+ dev_err(dev, "init phy%d err: %pe\n", i, ERR_PTR(err));
goto err_exit_phy;
}
}
err = reset_control_assert(rockchip->core_rst);
if (err) {
- dev_err(dev, "assert core_rst err %d\n", err);
+ dev_err(dev, "assert core_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
- dev_err(dev, "assert mgmt_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_sticky_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
- dev_err(dev, "assert pipe_rst err %d\n", err);
+ dev_err(dev, "assert pipe_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
@@ -221,19 +221,19 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_deassert(rockchip->pm_rst);
if (err) {
- dev_err(dev, "deassert pm_rst err %d\n", err);
+ dev_err(dev, "deassert pm_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_deassert(rockchip->aclk_rst);
if (err) {
- dev_err(dev, "deassert aclk_rst err %d\n", err);
+ dev_err(dev, "deassert aclk_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_deassert(rockchip->pclk_rst);
if (err) {
- dev_err(dev, "deassert pclk_rst err %d\n", err);
+ dev_err(dev, "deassert pclk_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
@@ -257,7 +257,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_power_on(rockchip->phys[i]);
if (err) {
- dev_err(dev, "power on phy%d err %d\n", i, err);
+ dev_err(dev, "power on phy%d err: %pe\n", i, ERR_PTR(err));
goto err_power_off_phy;
}
}
@@ -268,7 +268,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
RK_PHY_PLL_LOCK_SLEEP_US,
RK_PHY_PLL_LOCK_TIMEOUT_US);
if (err) {
- dev_err(dev, "PHY PLLs could not lock, %d\n", err);
+ dev_err(dev, "PHY PLLs could not lock: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
@@ -278,25 +278,25 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
*/
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_sticky_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->core_rst);
if (err) {
- dev_err(dev, "deassert core_rst err %d\n", err);
+ dev_err(dev, "deassert core_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
- dev_err(dev, "deassert mgmt_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
- dev_err(dev, "deassert pipe_rst err %d\n", err);
+ dev_err(dev, "deassert pipe_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
@@ -943,7 +943,7 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
struct pci_dev, bus_list);
ret = pci_reset_bus(dev);
if (ret)
- pci_warn(dev, "can't reset device: %d\n", ret);
+ pci_warn(dev, "can't reset device: %pe\n", ERR_PTR(ret));
break;
}
@@ -512,8 +512,8 @@ static struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev,
*/
rc = pci_doe_cache_protocols(doe_mb);
if (rc) {
- pci_err(pdev, "[%x] failed to cache protocols : %d\n",
- doe_mb->cap_offset, rc);
+ pci_err(pdev, "[%x] failed to cache protocols : %pe\n",
+ doe_mb->cap_offset, ERR_PTR(rc));
goto err_cancel;
}
@@ -738,14 +738,14 @@ static int pci_epf_mhi_core_init(struct pci_epf *epf)
ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no,
order_base_2(info->msi_count));
if (ret) {
- dev_err(dev, "Failed to set MSI configuration: %d\n", ret);
+ dev_err(dev, "Failed to set MSI configuration: %pe\n", ERR_PTR(ret));
return ret;
}
ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no,
epf->header);
if (ret) {
- dev_err(dev, "Failed to set Configuration header: %d\n", ret);
+ dev_err(dev, "Failed to set Configuration header: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -768,7 +768,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf)
if (info->flags & MHI_EPF_USE_DMA) {
ret = pci_epf_mhi_dma_init(epf_mhi);
if (ret) {
- dev_err(dev, "Failed to initialize DMA: %d\n", ret);
+ dev_err(dev, "Failed to initialize DMA: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -794,7 +794,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf)
/* Register the MHI EP controller */
ret = mhi_ep_register_controller(mhi_cntrl, info->config);
if (ret) {
- dev_err(dev, "Failed to register MHI EP controller: %d\n", ret);
+ dev_err(dev, "Failed to register MHI EP controller: %pe\n", ERR_PTR(ret));
if (info->flags & MHI_EPF_USE_DMA)
pci_epf_mhi_dma_deinit(epf_mhi);
return ret;
@@ -2129,7 +2129,7 @@ static int __init epf_ntb_init(void)
ret = pci_epf_register_driver(&epf_ntb_driver);
if (ret) {
destroy_workqueue(kpcintb_workqueue);
- pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
+ pr_err("Failed to register pci epf ntb driver: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -167,7 +167,7 @@ static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test,
ret = dma_submit_error(epf_test->transfer_cookie);
if (ret) {
- dev_err(dev, "Failed to do DMA tx_submit %d\n", ret);
+ dev_err(dev, "Failed to do DMA tx_submit: %pe\n", ERR_PTR(ret));
goto terminate;
}
@@ -949,7 +949,7 @@ static int __init pci_epf_test_init(void)
ret = pci_epf_register_driver(&test_driver);
if (ret) {
destroy_workqueue(kpcitest_workqueue);
- pr_err("Failed to register pci epf test driver --> %d\n", ret);
+ pr_err("Failed to register pci epf test driver: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1430,7 +1430,7 @@ static int __init epf_ntb_init(void)
ret = pci_epf_register_driver(&epf_ntb_driver);
if (ret) {
destroy_workqueue(kpcintb_workqueue);
- pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
+ pr_err("Failed to register pci epf ntb driver: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -727,8 +727,8 @@ static int __init pci_ep_cfs_init(void)
ret = configfs_register_subsystem(&pci_ep_cfs_subsys);
if (ret) {
- pr_err("Error %d while registering subsystem %s\n",
- ret, root->cg_item.ci_namebuf);
+ pr_err("Error while registering subsystem %s: %pe\n",
+ root->cg_item.ci_namebuf, ERR_PTR(ret));
goto err;
}
@@ -736,8 +736,8 @@ static int __init pci_ep_cfs_init(void)
&pci_functions_type);
if (IS_ERR(functions_group)) {
ret = PTR_ERR(functions_group);
- pr_err("Error %d while registering functions group\n",
- ret);
+ pr_err("Error while registering functions group: %pe\n",
+ ERR_PTR(ret));
goto err_functions_group;
}
@@ -746,8 +746,8 @@ static int __init pci_ep_cfs_init(void)
&pci_controllers_type);
if (IS_ERR(controllers_group)) {
ret = PTR_ERR(controllers_group);
- pr_err("Error %d while registering controllers group\n",
- ret);
+ pr_err("Error while registering controllers group: %pe\n",
+ ERR_PTR(ret));
goto err_controllers_group;
}
@@ -77,8 +77,8 @@ int pci_epf_bind(struct pci_epf *epf)
vfunc_no = epf_vf->vfunc_no;
if (vfunc_no < 1) {
- dev_err(dev, "Invalid virtual function number\n");
ret = -EINVAL;
+ dev_err(dev, "Invalid virtual function number: %pe\n", ERR_PTR(ret));
goto ret;
}
@@ -86,15 +86,15 @@ int pci_epf_bind(struct pci_epf *epf)
func_no = epf->func_no;
if (!IS_ERR_OR_NULL(epc)) {
if (!epc->max_vfs) {
- dev_err(dev, "No support for virt function\n");
ret = -EINVAL;
+ dev_err(dev, "No support for virt function: %pe\n", ERR_PTR(ret));
goto ret;
}
if (vfunc_no > epc->max_vfs[func_no]) {
- dev_err(dev, "PF%d: Exceeds max vfunc number\n",
- func_no);
ret = -EINVAL;
+ dev_err(dev, "PF%d: Exceeds max vfunc number: %pe\n",
+ func_no, ERR_PTR(ret));
goto ret;
}
}
@@ -103,15 +103,15 @@ int pci_epf_bind(struct pci_epf *epf)
func_no = epf->sec_epc_func_no;
if (!IS_ERR_OR_NULL(epc)) {
if (!epc->max_vfs) {
- dev_err(dev, "No support for virt function\n");
ret = -EINVAL;
+ dev_err(dev, "No support for virt function: %pe\n", ERR_PTR(ret));
goto ret;
}
if (vfunc_no > epc->max_vfs[func_no]) {
- dev_err(dev, "PF%d: Exceeds max vfunc number\n",
- func_no);
ret = -EINVAL;
+ dev_err(dev, "PF%d: Exceeds max vfunc number: %pe\n",
+ func_no, ERR_PTR(ret));
goto ret;
}
}
@@ -535,7 +535,7 @@ static int __init pci_epf_init(void)
ret = bus_register(&pci_epf_bus_type);
if (ret) {
- pr_err("failed to register pci epf bus --> %d\n", ret);
+ pr_err("failed to register pci epf bus: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -277,7 +277,7 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot,
if (retval == -EBUSY)
goto error_slot;
if (retval) {
- pr_err("pci_hp_register failed with error %d\n", retval);
+ pr_err("pci_hp_register failed with error: %pe\n", ERR_PTR(retval));
goto error_slot;
}
@@ -81,7 +81,7 @@ static int init_slot(struct controller *ctrl)
retval = pci_hp_initialize(&ctrl->hotplug_slot,
ctrl->pcie->port->subordinate, 0, name);
if (retval) {
- ctrl_err(ctrl, "pci_hp_initialize failed: error %d\n", retval);
+ ctrl_err(ctrl, "pci_hp_initialize failed with error: %pe\n", ERR_PTR(retval));
kfree(ops);
}
return retval;
@@ -210,21 +210,21 @@ static int pciehp_probe(struct pcie_device *dev)
if (rc == -EBUSY)
ctrl_warn(ctrl, "Slot already registered by another hotplug driver\n");
else
- ctrl_err(ctrl, "Slot initialization failed (%d)\n", rc);
+ ctrl_err(ctrl, "Slot initialization failed: %pe\n", ERR_PTR(rc));
goto err_out_release_ctlr;
}
/* Enable events after we have setup the data structures */
rc = pcie_init_notification(ctrl);
if (rc) {
- ctrl_err(ctrl, "Notification initialization failed (%d)\n", rc);
+ ctrl_err(ctrl, "Notification initialization failed: %d\n", rc);
goto err_out_free_ctrl_slot;
}
/* Publish to user space */
rc = pci_hp_add(&ctrl->hotplug_slot);
if (rc) {
- ctrl_err(ctrl, "Publication to user space failed (%d)\n", rc);
+ ctrl_err(ctrl, "Publication to user space failed: %pe\n", ERR_PTR(rc));
goto err_out_shutdown_notification;
}
@@ -104,8 +104,8 @@ static int init_slots(struct controller *ctrl)
retval = pci_hp_register(hotplug_slot,
ctrl->pci_dev->subordinate, slot->device, name);
if (retval) {
- ctrl_err(ctrl, "pci_hp_register failed with error %d\n",
- retval);
+ ctrl_err(ctrl, "pci_hp_register failed with error: %pe\n",
+ ERR_PTR(retval));
goto error_slotwq;
}
@@ -518,7 +518,7 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *
pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
__func__);
} else {
- dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
+ dev_err(&pdev->dev, "%s: failed with rc=%pe\n", __func__, ERR_PTR(rc));
}
return rc;
}
@@ -573,8 +573,8 @@ static int pci_parse_request_of_pci_ranges(struct device *dev,
case IORESOURCE_IO:
err = devm_pci_remap_iospace(dev, res, iobase);
if (err) {
- dev_warn(dev, "error %d: failed to map resource %pR\n",
- err, res);
+ dev_warn(dev, "failed to map resource %pR with error: %pe\n",
+ res, ERR_PTR(err));
resource_list_destroy_entry(win);
}
break;
@@ -1313,8 +1313,8 @@ static int pci_pm_runtime_suspend(struct device *dev)
pm->runtime_suspend, error);
return error;
} else if (error) {
- pci_err(pci_dev, "can't suspend (%ps returned %d)\n",
- pm->runtime_suspend, error);
+ pci_err(pci_dev, "can't suspend: %ps returned %pe)\n",
+ pm->runtime_suspend, ERR_PTR(error));
return error;
}
}
@@ -427,8 +427,8 @@ static int dpc_probe(struct pcie_device *dev)
dpc_handler, IRQF_SHARED,
"pcie-dpc", pdev);
if (status) {
- pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
- status);
+ pci_warn(pdev, "request IRQ%d failed: %pe\n", dev->irq,
+ ERR_PTR(status));
return status;
}
@@ -6019,7 +6019,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
ret = pci_reset_bus(pdev);
if (ret < 0)
- pci_err(pdev, "Failed to reset GPU: %d\n", ret);
+ pci_err(pdev, "Failed to reset GPU: %pe\n", ERR_PTR(ret));
}
iounmap(map);
@@ -2221,7 +2221,7 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
enable_all:
retval = pci_reenable_device(bridge);
if (retval)
- pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
+ pci_err(bridge, "Error reenabling bridge: %pe\n", ERR_PTR(retval));
pci_set_master(bridge);
}
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
@@ -343,8 +343,8 @@ void pci_hp_create_module_link(struct pci_slot *pci_slot)
return;
ret = sysfs_create_link(&pci_slot->kobj, kobj, "module");
if (ret)
- dev_err(&pci_slot->bus->dev, "Error creating sysfs link (%d)\n",
- ret);
+ dev_err(&pci_slot->bus->dev, "Error creating sysfs link: %pe\n",
+ ERR_PTR(ret));
kobject_put(kobj);
}
EXPORT_SYMBOL_GPL(pci_hp_create_module_link);
@@ -1542,7 +1542,7 @@ static int __init vga_arb_device_init(void)
rc = misc_register(&vga_arb_device);
if (rc < 0)
- pr_err("error %d registering device\n", rc);
+ pr_err("error registering device: %pe\n", ERR_PTR(rc));
bus_register_notifier(&pci_bus_type, &pci_notifier);