diff mbox series

[net-next,v2,6/7] net: ethernet: ti: cpsw_ale: add helper to setup classifier defaults

Message ID 20240628-am65-cpsw-multi-rx-v2-6-c399cb77db56@kernel.org (mailing list archive)
State New
Headers show
Series net: ethernet: ti: am65-cpsw: Add multi queue RX support | expand

Commit Message

Roger Quadros June 28, 2024, 12:01 p.m. UTC 
Default behaviour is to have 8 classifiers to map 8 DSCP/PCP
priorities to N receive threads (flows). N depends on number of
RX channels enabled for the port.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/net/ethernet/ti/cpsw_ale.c | 57 ++++++++++++++++++++++++++++++++++++++
 drivers/net/ethernet/ti/cpsw_ale.h |  1 +
 2 files changed, 58 insertions(+)

Comments

Simon Horman July 1, 2024, 7:35 a.m. UTC | #1 
On Fri, Jun 28, 2024 at 03:01:55PM +0300, Roger Quadros wrote:
> Default behaviour is to have 8 classifiers to map 8 DSCP/PCP
> priorities to N receive threads (flows). N depends on number of
> RX channels enabled for the port.
> 
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>  drivers/net/ethernet/ti/cpsw_ale.c | 57 ++++++++++++++++++++++++++++++++++++++
>  drivers/net/ethernet/ti/cpsw_ale.h |  1 +
>  2 files changed, 58 insertions(+)
> 
> diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
> index 75a17184d34c..51da527388df 100644
> --- a/drivers/net/ethernet/ti/cpsw_ale.c
> +++ b/drivers/net/ethernet/ti/cpsw_ale.c
> @@ -1650,3 +1650,60 @@ static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx,
>  	regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id);
>  	regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0);
>  }
> +
> +/* Disable all policer entries and thread mappings */
> +static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
> +{
> +	int i;
> +
> +	for (i = 0; i < ale->params.num_policers ; i++) {
> +		cpsw_ale_policer_read_idx(ale, i);
> +		regmap_field_write(ale->fields[POL_PORT_MEN], 0);
> +		regmap_field_write(ale->fields[POL_PRI_MEN], 0);
> +		regmap_field_write(ale->fields[POL_OUI_MEN], 0);
> +		regmap_field_write(ale->fields[POL_DST_MEN], 0);
> +		regmap_field_write(ale->fields[POL_SRC_MEN], 0);
> +		regmap_field_write(ale->fields[POL_OVLAN_MEN], 0);
> +		regmap_field_write(ale->fields[POL_IVLAN_MEN], 0);
> +		regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0);
> +		regmap_field_write(ale->fields[POL_IPSRC_MEN], 0);
> +		regmap_field_write(ale->fields[POL_IPDST_MEN], 0);
> +		regmap_field_write(ale->fields[POL_EN], 0);
> +		regmap_field_write(ale->fields[POL_RED_DROP_EN], 0);
> +		regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0);
> +		regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0);
> +
> +		cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0);
> +	}
> +}
> +
> +/* Default classifer is to map 8 user priorities to N receive channels */
> +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
> +{
> +	int pri, idx;
> +	int pri_thread_map[8][9] = {	{ 0, 0, 0, 0, 0, 0, 0, 0, },
> +					{ 0, 0, 0, 0, 1, 1, 1, 1, },
> +					{ 0, 0, 0, 0, 1, 1, 2, 2, },
> +					{ 1, 0, 0, 1, 2, 2, 3, 3, },
> +					{ 1, 0, 0, 1, 2, 3, 4, 4, },
> +					{ 1, 0, 0, 2, 3, 4, 5, 5, },
> +					{ 1, 0, 0, 2, 3, 4, 5, 6, },
> +					{ 2, 0, 1, 3, 4, 5, 6, 7, } };

Hi Roger,

Perhaps it is obvious, but I'm wondering if it is appropriate
to add a comment explaining the layout of the table, especially
the latter rows where the mapping of priority to receive channel
seems somewhat non-trivial.

> +
> +	cpsw_ale_policer_reset(ale);
> +
> +	/* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */
> +	for (pri = 0; pri < 8; pri++) {
> +		idx = pri;
> +
> +		/* Classifier 'idx' match on priority 'pri' */
> +		cpsw_ale_policer_read_idx(ale, idx);
> +		regmap_field_write(ale->fields[POL_PRI_VAL], pri);
> +		regmap_field_write(ale->fields[POL_PRI_MEN], 1);
> +		cpsw_ale_policer_write_idx(ale, idx);
> +
> +		/* Map Classifier 'idx' to thread provided by the map */
> +		cpsw_ale_policer_thread_idx_enable(ale, idx,
> +						   pri_thread_map[num_rx_ch - 1][pri], 1);
> +	}
> +}
> diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
> index 2cb76acc6d16..1e4e9a3dd234 100644
> --- a/drivers/net/ethernet/ti/cpsw_ale.h
> +++ b/drivers/net/ethernet/ti/cpsw_ale.h
> @@ -193,5 +193,6 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
>  int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
>  void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
>  			      bool add);
> +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch);
>  
>  #endif
> 
> -- 
> 2.34.1
> 
>
Roger Quadros July 1, 2024, 10:32 a.m. UTC | #2 
On 01/07/2024 10:35, Simon Horman wrote:
> On Fri, Jun 28, 2024 at 03:01:55PM +0300, Roger Quadros wrote:
>> Default behaviour is to have 8 classifiers to map 8 DSCP/PCP
>> priorities to N receive threads (flows). N depends on number of
>> RX channels enabled for the port.
>>
>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>> ---
>>  drivers/net/ethernet/ti/cpsw_ale.c | 57 ++++++++++++++++++++++++++++++++++++++
>>  drivers/net/ethernet/ti/cpsw_ale.h |  1 +
>>  2 files changed, 58 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
>> index 75a17184d34c..51da527388df 100644
>> --- a/drivers/net/ethernet/ti/cpsw_ale.c
>> +++ b/drivers/net/ethernet/ti/cpsw_ale.c
>> @@ -1650,3 +1650,60 @@ static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx,
>>  	regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id);
>>  	regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0);
>>  }
>> +
>> +/* Disable all policer entries and thread mappings */
>> +static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < ale->params.num_policers ; i++) {
>> +		cpsw_ale_policer_read_idx(ale, i);
>> +		regmap_field_write(ale->fields[POL_PORT_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_PRI_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_OUI_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_DST_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_SRC_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_OVLAN_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_IVLAN_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_IPSRC_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_IPDST_MEN], 0);
>> +		regmap_field_write(ale->fields[POL_EN], 0);
>> +		regmap_field_write(ale->fields[POL_RED_DROP_EN], 0);
>> +		regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0);
>> +		regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0);
>> +
>> +		cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0);
>> +	}
>> +}
>> +
>> +/* Default classifer is to map 8 user priorities to N receive channels */
>> +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
>> +{
>> +	int pri, idx;
>> +	int pri_thread_map[8][9] = {	{ 0, 0, 0, 0, 0, 0, 0, 0, },
>> +					{ 0, 0, 0, 0, 1, 1, 1, 1, },
>> +					{ 0, 0, 0, 0, 1, 1, 2, 2, },
>> +					{ 1, 0, 0, 1, 2, 2, 3, 3, },
>> +					{ 1, 0, 0, 1, 2, 3, 4, 4, },
>> +					{ 1, 0, 0, 2, 3, 4, 5, 5, },
>> +					{ 1, 0, 0, 2, 3, 4, 5, 6, },
>> +					{ 2, 0, 1, 3, 4, 5, 6, 7, } };
> 
> Hi Roger,
> 
> Perhaps it is obvious, but I'm wondering if it is appropriate
> to add a comment explaining the layout of the table, especially
> the latter rows where the mapping of priority to receive channel
> seems somewhat non-trivial.

Sure. I took the table straight off from the All new switch book. [1]

Priorities 3 to 7 are straight forward. Priorities 0 to 2 are listed like so in
decreasing order of priority

0 (default)	Best Effort
2 		Spare (undefined)
1 (lowest)	Background

[1] Table 13-2 IEEE 802.1p Recommended Priority Mappings to Class of Service.

> 
>> +
>> +	cpsw_ale_policer_reset(ale);
>> +
>> +	/* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */
>> +	for (pri = 0; pri < 8; pri++) {
>> +		idx = pri;
>> +
>> +		/* Classifier 'idx' match on priority 'pri' */
>> +		cpsw_ale_policer_read_idx(ale, idx);
>> +		regmap_field_write(ale->fields[POL_PRI_VAL], pri);
>> +		regmap_field_write(ale->fields[POL_PRI_MEN], 1);
>> +		cpsw_ale_policer_write_idx(ale, idx);
>> +
>> +		/* Map Classifier 'idx' to thread provided by the map */
>> +		cpsw_ale_policer_thread_idx_enable(ale, idx,
>> +						   pri_thread_map[num_rx_ch - 1][pri], 1);
>> +	}
>> +}
>> diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
>> index 2cb76acc6d16..1e4e9a3dd234 100644
>> --- a/drivers/net/ethernet/ti/cpsw_ale.h
>> +++ b/drivers/net/ethernet/ti/cpsw_ale.h
>> @@ -193,5 +193,6 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
>>  int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
>>  void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
>>  			      bool add);
>> +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch);
>>  
>>  #endif
>>
>> -- 
>> 2.34.1
>>
>>
Simon Horman July 2, 2024, 9:24 a.m. UTC | #3 
On Mon, Jul 01, 2024 at 01:32:08PM +0300, Roger Quadros wrote:
> 
> On 01/07/2024 10:35, Simon Horman wrote:
> > On Fri, Jun 28, 2024 at 03:01:55PM +0300, Roger Quadros wrote:
> >> Default behaviour is to have 8 classifiers to map 8 DSCP/PCP
> >> priorities to N receive threads (flows). N depends on number of
> >> RX channels enabled for the port.
> >>
> >> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> >> ---
> >>  drivers/net/ethernet/ti/cpsw_ale.c | 57 ++++++++++++++++++++++++++++++++++++++
> >>  drivers/net/ethernet/ti/cpsw_ale.h |  1 +
> >>  2 files changed, 58 insertions(+)
> >>
> >> diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
> >> index 75a17184d34c..51da527388df 100644
> >> --- a/drivers/net/ethernet/ti/cpsw_ale.c
> >> +++ b/drivers/net/ethernet/ti/cpsw_ale.c
> >> @@ -1650,3 +1650,60 @@ static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx,
> >>  	regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id);
> >>  	regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0);
> >>  }
> >> +
> >> +/* Disable all policer entries and thread mappings */
> >> +static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
> >> +{
> >> +	int i;
> >> +
> >> +	for (i = 0; i < ale->params.num_policers ; i++) {
> >> +		cpsw_ale_policer_read_idx(ale, i);
> >> +		regmap_field_write(ale->fields[POL_PORT_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_PRI_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_OUI_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_DST_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_SRC_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_OVLAN_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_IVLAN_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_IPSRC_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_IPDST_MEN], 0);
> >> +		regmap_field_write(ale->fields[POL_EN], 0);
> >> +		regmap_field_write(ale->fields[POL_RED_DROP_EN], 0);
> >> +		regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0);
> >> +		regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0);
> >> +
> >> +		cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0);
> >> +	}
> >> +}
> >> +
> >> +/* Default classifer is to map 8 user priorities to N receive channels */
> >> +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
> >> +{
> >> +	int pri, idx;
> >> +	int pri_thread_map[8][9] = {	{ 0, 0, 0, 0, 0, 0, 0, 0, },
> >> +					{ 0, 0, 0, 0, 1, 1, 1, 1, },
> >> +					{ 0, 0, 0, 0, 1, 1, 2, 2, },
> >> +					{ 1, 0, 0, 1, 2, 2, 3, 3, },
> >> +					{ 1, 0, 0, 1, 2, 3, 4, 4, },
> >> +					{ 1, 0, 0, 2, 3, 4, 5, 5, },
> >> +					{ 1, 0, 0, 2, 3, 4, 5, 6, },
> >> +					{ 2, 0, 1, 3, 4, 5, 6, 7, } };
> > 
> > Hi Roger,
> > 
> > Perhaps it is obvious, but I'm wondering if it is appropriate
> > to add a comment explaining the layout of the table, especially
> > the latter rows where the mapping of priority to receive channel
> > seems somewhat non-trivial.
> 
> Sure. I took the table straight off from the All new switch book. [1]
> 
> Priorities 3 to 7 are straight forward. Priorities 0 to 2 are listed like so in
> decreasing order of priority
> 
> 0 (default)	Best Effort
> 2 		Spare (undefined)
> 1 (lowest)	Background
> 
> [1] Table 13-2 IEEE 802.1p Recommended Priority Mappings to Class of Service.

Thanks Roger,

I was able to correlate this with tables G-2 and G-3 of 802.1D-2004.

I do think it would be adding some sort of comment to the code
about this.

...
diff mbox series

Patch

diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
index 75a17184d34c..51da527388df 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c
@@ -1650,3 +1650,60 @@  static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx,
 	regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id);
 	regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0);
 }
+
+/* Disable all policer entries and thread mappings */
+static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
+{
+	int i;
+
+	for (i = 0; i < ale->params.num_policers ; i++) {
+		cpsw_ale_policer_read_idx(ale, i);
+		regmap_field_write(ale->fields[POL_PORT_MEN], 0);
+		regmap_field_write(ale->fields[POL_PRI_MEN], 0);
+		regmap_field_write(ale->fields[POL_OUI_MEN], 0);
+		regmap_field_write(ale->fields[POL_DST_MEN], 0);
+		regmap_field_write(ale->fields[POL_SRC_MEN], 0);
+		regmap_field_write(ale->fields[POL_OVLAN_MEN], 0);
+		regmap_field_write(ale->fields[POL_IVLAN_MEN], 0);
+		regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0);
+		regmap_field_write(ale->fields[POL_IPSRC_MEN], 0);
+		regmap_field_write(ale->fields[POL_IPDST_MEN], 0);
+		regmap_field_write(ale->fields[POL_EN], 0);
+		regmap_field_write(ale->fields[POL_RED_DROP_EN], 0);
+		regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0);
+		regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0);
+
+		cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0);
+	}
+}
+
+/* Default classifer is to map 8 user priorities to N receive channels */
+void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
+{
+	int pri, idx;
+	int pri_thread_map[8][9] = {	{ 0, 0, 0, 0, 0, 0, 0, 0, },
+					{ 0, 0, 0, 0, 1, 1, 1, 1, },
+					{ 0, 0, 0, 0, 1, 1, 2, 2, },
+					{ 1, 0, 0, 1, 2, 2, 3, 3, },
+					{ 1, 0, 0, 1, 2, 3, 4, 4, },
+					{ 1, 0, 0, 2, 3, 4, 5, 5, },
+					{ 1, 0, 0, 2, 3, 4, 5, 6, },
+					{ 2, 0, 1, 3, 4, 5, 6, 7, } };
+
+	cpsw_ale_policer_reset(ale);
+
+	/* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */
+	for (pri = 0; pri < 8; pri++) {
+		idx = pri;
+
+		/* Classifier 'idx' match on priority 'pri' */
+		cpsw_ale_policer_read_idx(ale, idx);
+		regmap_field_write(ale->fields[POL_PRI_VAL], pri);
+		regmap_field_write(ale->fields[POL_PRI_MEN], 1);
+		cpsw_ale_policer_write_idx(ale, idx);
+
+		/* Map Classifier 'idx' to thread provided by the map */
+		cpsw_ale_policer_thread_idx_enable(ale, idx,
+						   pri_thread_map[num_rx_ch - 1][pri], 1);
+	}
+}
diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
index 2cb76acc6d16..1e4e9a3dd234 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.h
+++ b/drivers/net/ethernet/ti/cpsw_ale.h
@@ -193,5 +193,6 @@  int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
 int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
 			      bool add);
+void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch);
 
 #endif