@@ -157,6 +157,56 @@ static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
return 0;
}
+#if 0 /* DM365 */
+#define EMAC_BASE (0x01D07000)
+#define EMAC_CNTRL_OFFSET (0x0000)
+#define PHY_ADDR 1
+#endif
+
+#if 1 /* DA8XX */
+#define EMAC_BASE (0x01e20000)
+#define EMAC_CNTRL_OFFSET (0x3000)
+#define PHY_ADDR 1 /* 1-3 is ok on da830 evm */
+#endif
+
+#define EMAC_SOFTRESET (0x174)
+#define PHY_REG MII_PHYSID1
+
+static void mdio_emac_soft_reset_test(struct davinci_mdio_data *data)
+{
+ struct davinci_mdio_regs __iomem *regs = data->regs;
+ int loops = 0, status_ok = 0;
+ void __iomem *emac;
+ u32 reg;
+
+ emac = ioremap(EMAC_BASE + EMAC_CNTRL_OFFSET, SZ_4K);
+ if (WARN_ON(!emac))
+ return;
+
+ for (loops = 0; loops < 10000; loops++) {
+ while (__raw_readl(®s->user[0].access) &
+ USERACCESS_GO)
+ ;
+
+ reg = (USERACCESS_GO | USERACCESS_READ |
+ (PHY_REG << 21) | (PHY_ADDR << 16));
+ __raw_writel(reg, ®s->user[0].access);
+
+ while (__raw_readl(®s->user[0].access) &
+ USERACCESS_GO) {
+ __raw_writel(1, emac + EMAC_SOFTRESET);
+ if (__raw_readl(®s->control) & CONTROL_IDLE) {
+ printk(KERN_ERR "idle triggered!!\n");
+ return;
+ }
+ }
+ if (__raw_readl(®s->user[0].access) & USERACCESS_ACK)
+ status_ok++;
+ }
+ printk(KERN_ERR "%d test loops completed, %d reads ok\n", loops,
+ status_ok);
+}
+
static int __devinit davinci_mdio_probe(struct platform_device *pdev)
{
struct mdio_platform_data *pdata = pdev->dev.platform_data;
@@ -262,6 +312,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
}
data->bus->phy_mask = phy_mask;
+ mdio_emac_soft_reset_test(data);
+
/* register the mii bus */
ret = mdiobus_register(data->bus);
if (ret)