From patchwork Mon Jul 30 23:26:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 1256751 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 0E5483FCC5 for ; Mon, 30 Jul 2012 23:27:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755097Ab2G3X1C (ORCPT ); Mon, 30 Jul 2012 19:27:02 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:50206 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754975Ab2G3X1B (ORCPT ); Mon, 30 Jul 2012 19:27:01 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6UNQrwU010023; Mon, 30 Jul 2012 18:26:54 -0500 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6UNQrgo015211; Mon, 30 Jul 2012 18:26:53 -0500 Received: from [172.24.112.214] (172.24.112.214) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Mon, 30 Jul 2012 18:26:53 -0500 Message-ID: <50171841.40309@ti.com> Date: Mon, 30 Jul 2012 18:26:57 -0500 From: Jon Hunter User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Paul Walmsley CC: linux-omap , linux-arm , Ming Lei , Will Deacon , Benoit Cousson , Kevin Hilman Subject: Re: [PATCH V2 08/10] ARM: OMAP4: Prevent EMU power domain transitioning to OFF when in-use References: <1339104132-26885-1-git-send-email-jon-hunter@ti.com> <1339104132-26885-9-git-send-email-jon-hunter@ti.com> <500028B3.1040309@ti.com> <50045D17.9050704@ti.com> In-Reply-To: X-Originating-IP: [172.24.112.214] Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hi Paul, On 07/16/2012 01:38 PM, Paul Walmsley wrote: > Hi Jon, > > On Mon, 16 Jul 2012, Jon Hunter wrote: > >> Yes I see that makes sense. However, patch #7 has already changed the >> mapping of the flags. I had intended that patch #7 and #8 would be >> applied together. However, I could see that patch #7 can be taken just >> to eliminate using the SW_SLEEP state. So basically, what I am saying is >> does patch #7 have any value without #8? > > Certainly not as much value as it had before. But my understanding, which > is possibly incorrect, matches what you wrote in patch #7's description: > > "For OMAP4 devices, SW_SLEEP is equivalent to HW_AUTO and NO_SLEEP is > equivalent to SW_WKUP. The only difference between HW_AUTO and SW_SLEEP > for OMAP4 devices is that the PRM_IRQSTATUS_MPU.TRANSITION_ST interrupt > status is set in case of SW_SLEEP transition, and not set in case of > HW_AUTO transition." > > We don't use that PRM_IRQSTATUS_MPU.TRANSITION_ST interrupt bit. So if > SW_SLEEP and HW_AUTO really have identical meanings otherwise, then I > suppose we might as well use the one that does what we need with no > extraneous side-effects? My recollection from a conversation with Benoît > a few months ago was that this was his view as well. > >> That's fine with me. We can always workaround such issues by adding flags. >> >> I can give this a try this week and let you know how it goes. > > Okay, great. No rush on my account. I have been testing your patch [1] on OMAP3 and found that the EMU clock domain was not being disabled for two reasons. 1. When HWMOD attempts to disable the clock domain for OMAP2/3 devices we simply return without doing anything. Not sure if it is safe to remove this but I can do some more testing on OMAP2/3. commit a0307bd539ecef976793679a1c4ff0d47b22c4bd Author: Jon Hunter Date: Mon Jul 30 18:04:06 2012 -0500 ARM: OMAP2/3: Allow HWMOD to disable clock domains Currently when HWMOD attempts to disable a clock domain on OMAP2/3 devices we will return from the function clkdm_hwmod_disable() without actually disabling the clock domain. Per the comment this is deliberate because initially HWMOD OMAP2/3 devices did not support clock domains. However, clock domains are now supported by HWMOD for these devices and so allow HWMOD to disable the clock domains. XXX - Tested on OMAP3430 beagle board, but needs more testing on OMAP2/3 I need to do more testing but wanted to give you this feedback and get your comments. Cheers Jon [1] http://marc.info/?l=linux-arm-kernel&m=134212814812557&w=2 --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 011186f..8f7a941 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1075,10 +1075,6 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh) */ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) { - /* The clkdm attribute does not exist yet prior OMAP4 */ - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return 0; - /* * XXX Rewrite this code to maintain a list of enabled * downstream hwmods for debugging purposes? 2. I need to make the following changes to your patch. The change to omap2_clkdm_clk_disable() was needed to get the EMU to turn off. At the same time I thought we should make the same change to omap2_clkdm_clk_enable(). diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index 09385a9..c94b2fb 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -223,7 +223,8 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm) _enable_hwsup(clkdm); } else { if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap2_clkdm_wakeup(clkdm); + (cpu_is_omap24xx()) ? omap2_clkdm_wakeup(clkdm) : + omap3_clkdm_wakeup(clkdm); } return 0; @@ -257,7 +258,8 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm) _enable_hwsup(clkdm); } else { if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) - omap2_clkdm_sleep(clkdm); + (cpu_is_omap24xx()) ? omap2_clkdm_sleep(clkdm) : + omap3_clkdm_sleep(clkdm); }