From patchwork Mon Oct 8 11:33:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 1565161 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 43C79DFFAD for ; Mon, 8 Oct 2012 11:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752037Ab2JHLdL (ORCPT ); Mon, 8 Oct 2012 07:33:11 -0400 Received: from service87.mimecast.com ([91.220.42.44]:52638 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751553Ab2JHLdL (ORCPT ); Mon, 8 Oct 2012 07:33:11 -0400 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 08 Oct 2012 12:33:08 +0100 Received: from [10.1.70.21] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 8 Oct 2012 12:33:06 +0100 Message-ID: <5072B9EF.1020005@arm.com> Date: Mon, 08 Oct 2012 12:33:03 +0100 From: Marc Zyngier User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: Tony Lindgren CC: Dave Martin , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Nicolas Pitre , Russell King - ARM Linux Subject: Re: [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode References: <1347036934-8519-1-git-send-email-marc.zyngier@arm.com> <1347036934-8519-3-git-send-email-marc.zyngier@arm.com> <20121005200822.GQ3874@atomide.com> <6d3553bfe8a2d1ac88cab852100616a7@localhost> <20121006160031.GC3874@atomide.com> <20121008110109.GE2302@linaro.org> In-Reply-To: <20121008110109.GE2302@linaro.org> X-Enigmail-Version: 1.5a1pre X-OriginalArrivalTime: 08 Oct 2012 11:33:06.0312 (UTC) FILETIME=[AF6EE080:01CDA548] X-MC-Unique: 112100812330807601 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On 08/10/12 12:01, Dave Martin wrote: > On Sat, Oct 06, 2012 at 09:00:32AM -0700, Tony Lindgren wrote: >> * Marc Zyngier [121006 03:19]: >>> >>> If so, that indicates some side effect of the safe_svcmode_maskall macro, >>> and I suspect the "movs pc, lr" bit. >>> >>> Can you try the attached patch? It basically falls back to the previous >>> behaviour if not entered in HYP mode. >> ... >> >>> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h >>> index 658a15d..b21b97f 100644 >>> --- a/arch/arm/include/asm/assembler.h >>> +++ b/arch/arm/include/asm/assembler.h >>> @@ -254,16 +254,17 @@ >>> mov lr , \reg >>> and lr , lr , #MODE_MASK >>> cmp lr , #HYP_MODE >>> - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT >>> + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT >>> bic \reg , \reg , #MODE_MASK >>> orr \reg , \reg , #SVC_MODE >>> THUMB( orr \reg , \reg , #PSR_T_BIT ) >>> - msr spsr_cxsf, \reg >>> - adr lr, BSYM(2f) >>> bne 1f >>> + orr \reg, \reg, #PSR_A_BIT >>> + adr lr, BSYM(2f) >>> + msr spsr_cxsf, \reg >>> __MSR_ELR_HYP(14) >>> __ERET >>> -1: movs pc, lr >>> +1: msr cpsr_c, \reg >>> 2: >>> .endm >>> >> >> The minimal version of this that still boots on my n800 is just >> the last change of the above patch: >> >> --- a/arch/arm/include/asm/assembler.h >> +++ b/arch/arm/include/asm/assembler.h >> @@ -263,7 +263,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) >> bne 1f >> __MSR_ELR_HYP(14) >> __ERET >> -1: movs pc, lr >> +1: msr cpsr_c, \reg >> 2: >> .endm >> > > In an attempt to narrow this down... > > Can you follow this (i.e., _after_ a known successful switch to SVC mode) > > (a) > mrs \reg, cpsr > msr spsr_cxsf, \reg > adr \reg, 3f > movs pc, lr > 3: > > and (b) > > mrs \reg, cpsr > orr \reg, \reg, #CPSR_A_BIT > msr cpsr_cxsf, \reg > > and (c) > > mrs \reg, cpsr > orr \reg, \reg, #CPSR_A_BIT > msr spsr_cxsf, \reg > adr \reg, 3f > movs pc, lr > 3: > > > > > If only (a) works, this would suggest that the attempt to set the A bit > is causing the problem. > > If only (b) works, this suggests that the A bit is OK but that some > invalid hardware state, or something else we don't understand, is causing > exception returns to fail in general. > > If (a) and (b) work but (c) fails, this suggests that specifically > trying to set the A bit via an exception return is problematic. > > If all of them work then this suggests some invalid hardware state or > something else we don't understand, but which is cleared by the initial > msr cpsr_c which clobbers the processor mode. Playing with an Integrator-CP with a 1136 tile, the only way I could cause the thing to fail was to boot the thing in SYSTEM mode. Tony, can you possibly also try the attached patch? Thanks, M. diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 683a1e6..7714ec7 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -253,6 +253,8 @@ mrs \reg , cpsr mov lr , \reg and lr , lr , #MODE_MASK + cmp lr , #SYSTEM_MODE /* Yet another braindead platform? */ + beq omgsys cmp lr , #HYP_MODE orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT bic \reg , \reg , #MODE_MASK @@ -264,6 +266,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) __MSR_ELR_HYP(14) __ERET 1: movs pc, lr +omgsys: msr cpsr_c, \reg 2: .endm