From patchwork Thu Oct 25 07:00:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1642161 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 2E7DB3FD4E for ; Thu, 25 Oct 2012 07:00:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757836Ab2JYHAn (ORCPT ); Thu, 25 Oct 2012 03:00:43 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:49258 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757458Ab2JYHAm (ORCPT ); Thu, 25 Oct 2012 03:00:42 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9P70XWn008516; Thu, 25 Oct 2012 02:00:34 -0500 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9P70TK1024791; Thu, 25 Oct 2012 12:30:30 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Thu, 25 Oct 2012 12:30:29 +0530 Received: from [172.24.136.169] (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9P70NYb028909; Thu, 25 Oct 2012 12:30:23 +0530 Message-ID: <5088E387.2050704@ti.com> Date: Thu, 25 Oct 2012 12:30:23 +0530 From: Santosh Shilimkar User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120912 Thunderbird/15.0.1 MIME-Version: 1.0 To: Jon Hunter , Kevin Hilman CC: Paul Walmsley , Linus Walleij , Felipe Balbi , Igor Grinberg , , , Grazvydas Ignotas Subject: Re: [PATCH v2] gpio/omap: fix off-mode bug: clear debounce clock enable mask on free/reset References: <1351098641-23917-1-git-send-email-khilman@deeprootsystems.com> <50887197.8010104@ti.com> In-Reply-To: <50887197.8010104@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On Thursday 25 October 2012 04:24 AM, Jon Hunter wrote: > > On 10/24/2012 12:10 PM, Kevin Hilman wrote: >> From: Kevin Hilman >> >> When a GPIO bank is freed or shutdown, ensure that the banks >> dbck_enable_mask is cleared also. Otherwise, context restore on >> subsequent off-mode transition will restore previous value from the >> shadow copies (bank->context.debounce*) leading to mismatch state >> between driver state and hardware state. >> >> This was discovered when board code was doing >> >> gpio_request_one() >> gpio_set_debounce() >> gpio_free() >> >> which was leaving the GPIO debounce settings in a confused state. If >> that GPIO bank is subsequently used with off-mode enabled, bogus state >> would be restored, leaving GPIO debounce enabled which then prevented >> the CORE powerdomain from transitioning. >> >> To fix, ensure that bank->dbck_enable_mask is cleared when the bank >> is freed/shutdown so debounce state doesn't persist. >> The freed part is fine but I don't understand why it needs to be done on _a_ gpio irq shutdown callback where IRQs related configuration on that one GPIO needs to be cleared. De-bounce clock is surely not IRQ related configuration. >> Special thanks to Grazvydas Ignotas for pointing out a bug in an >> earlier version that would've disabled debounce on any runtime PM >> transition. >> >> Reported-by: Paul Walmsley >> Cc: Igor Grinberg >> Cc: Grazvydas Ignotas >> Signed-off-by: Kevin Hilman >> --- >> v2: only clear mask in free/shutdown, not in runtime PM paths, >> clarified changelog >> Applies on v3.7-rc2. >> >> drivers/gpio/gpio-omap.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c >> index 94cbc84..113b167 100644 >> --- a/drivers/gpio/gpio-omap.c >> +++ b/drivers/gpio/gpio-omap.c >> @@ -539,6 +539,7 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio) >> _set_gpio_irqenable(bank, gpio, 0); >> _clear_gpio_irqstatus(bank, gpio); >> _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); >> + bank->dbck_enable_mask = 0; >> } > > Does this need to be ... > > + bank->dbck_enable_mask &= ~(GPIO_BIT(bank, gpio)); > + _gpio_dbck_disable(bank); > Yes, its a per bank clock. There is an alternate. See below. > There could be more than one gpio using debounce and so we should only > clear the appropriate bit. Also after clearing a bit we could see if we > can disable the debounce clock too. > When I mentioned the clearing in gpio_free() path will do trick, I had something like below in mind. /* This patch should be enough according to me unless and until I am missing mask clear need in irq_shutdown path. It will also take care of disabling of debounce clock as part of runtime suspend callback. Regards, Santosh --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index dee2856..8574105 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -629,8 +629,10 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) * If this is the last gpio to be freed in the bank, * disable the bank module. */ - if (!bank->mod_usage) + if (!bank->mod_usage) { + bank->dbck_enable_mask = 0; pm_runtime_put(bank->dev); + } }