From patchwork Fri Mar 18 10:13:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 8617921 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EA8B6C0553 for ; Fri, 18 Mar 2016 10:14:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DE49620374 for ; Fri, 18 Mar 2016 10:14:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C4AD8202E9 for ; Fri, 18 Mar 2016 10:14:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754729AbcCRKOK (ORCPT ); Fri, 18 Mar 2016 06:14:10 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16079 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753638AbcCRKOI (ORCPT ); Fri, 18 Mar 2016 06:14:08 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 18 Mar 2016 03:14:22 -0700 Received: from HQMAIL108.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 18 Mar 2016 03:13:13 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 18 Mar 2016 03:13:13 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 18 Mar 2016 10:14:02 +0000 Received: from [10.21.132.114] (10.21.132.114) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 18 Mar 2016 10:13:58 +0000 Subject: Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document To: Geert Uytterhoeven References: <1458224359-32665-1-git-send-email-jonathanh@nvidia.com> <1458224359-32665-15-git-send-email-jonathanh@nvidia.com> CC: Thomas Gleixner , Jason Cooper , Marc Zyngier , =?UTF-8?Q?Beno=c3=aet_Cousson?= , Tony Lindgren , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , "Kumar Gala" , Stephen Warren , "Thierry Reding" , Kevin Hilman , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , "linux-omap@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" From: Jon Hunter Message-ID: <56EBD4E5.1060002@nvidia.com> Date: Fri, 18 Mar 2016 10:13:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.21.132.114] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 18/03/16 09:13, Geert Uytterhoeven wrote: > Hi Jon, > > On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter wrote: >> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power >> Domain properties") documented optional clock and power-dmoain properties >> for the ARM GIC. Currently, there are no users of these and for the >> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a >> functional clock and interface clock, that need to be enabled. > > The reason that there are no users for this is twofold: > 1. The GIC driver doesn't have Runtime PM support yet, > 2. There was no clean way to prevent the GIC's clock from being disabled. > Due to this, adding the clocks to the DTSes would mean that they will be > disabled during boot up as unused clocks, leading to a system lock-up. > > I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch, > but unfortunately it seems the platform driver only supports non-root > controllers, while the r8a7791 GIC is the primary one... Can you try making the following change ... > Alternatively, part 2 can to be fixed by "clk: introduce CLK_ENABLE_HAND_OFF > flag", combined with the clock driver setting the flag when needed. > Unfortunately that patch is not yet upstream, and not even in -next. > Note that drivers/clk/renesas/renesas-cpg-mssr.c already handles > CLK_ENABLE_HAND_OFF if present, and else just ignores the clock. > So I could already add the clock to r8a7795.dtsi, which uses that driver. > > For older SoCs, the module clocks are described in the dtsi, and I would need a > crude hack to enable CLK_ENABLE_HAND_OFF in the clock driver. > >> To allow flexibility, drop the 'clock-names' from the GIC binding and >> just provide a list of clocks which the driver can parse. It is assumed >> that any clocks that are listed, need to be enabled in order to access >> the GIC. > > Originally I just wanted to have "clocks", and let the details be handled by > SoC-specific code. However, Mark Rutland insisted on using the clock naming > from the GIC TRMs, as the number of clocks and their names depend on the > GIC variant. > > Apparently they also depend on the SoC... Yes this case is a little different because the GIC is a 2nd level GIC. Cheers Jon --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 9e7cf7abf757..2e971e600036 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1372,7 +1372,7 @@ static int gic_probe(struct platform_device *pdev) void __iomem *dist_base; void __iomem *cpu_base; u32 percpu_offset; - int ret, irq; + int ret, irq = 0; if (dev->of_node == NULL) return -EINVAL; @@ -1393,11 +1393,8 @@ static int gic_probe(struct platform_device *pdev) if (ret < 0) goto rpm_disable; - irq = irq_of_parse_and_map(dev->of_node, 0); - if (!irq) { - ret = -EINVAL; - goto rpm_put; - } + if (of_irq_count(dev->of_node) > 0) + irq = irq_of_parse_and_map(dev->of_node, 0); ret = gic_of_setup(dev->of_node, &dist_base, &cpu_base, &percpu_offset); if (ret) @@ -1411,7 +1408,8 @@ static int gic_probe(struct platform_device *pdev) gic->chip.parent = dev; - irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, gic); + if (irq) + irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, gic); pm_runtime_put(dev); @@ -1424,7 +1422,6 @@ gic_unmap: iounmap(cpu_base); irq_dispose: irq_dispose_mapping(irq); -rpm_put: pm_runtime_put_sync(dev); rpm_disable: pm_runtime_disable(dev);