===================================================================
@@ -379,6 +379,51 @@ static void sr_configure(struct omap_sr
sr->is_sr_reset = 0;
}
+static int sr_reset_voltage(int srid)
+{
+ u32 target_opp_no, vsel = 0;
+ u32 reg_addr = 0;
+ u32 loop_cnt = 0, retries_cnt = 0;
+ u32 vc_bypass_value;
+
+ if (srid == SR1) {
+ target_opp_no = resource_get_level("vdd1_opp");
+ vsel = mpu_opps[target_opp_no].vsel;
+ reg_addr = R_VDD1_SR_CONTROL;
+ } else if (srid == SR2) {
+ target_opp_no = resource_get_level("vdd2_opp");
+ vsel = l3_opps[target_opp_no].vsel;
+ reg_addr = R_VDD2_SR_CONTROL;
+ }
+
+ vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
+ (reg_addr << OMAP3430_REGADDR_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
+
+ prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+
+ vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+
+ while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
+ loop_cnt++;
+ if (retries_cnt > 10) {
+ printk(KERN_INFO "Loop count exceeded in check SR I2C"
+ "write\n");
+ return SR_FAIL;
+ }
+ if (loop_cnt > 50) {
+ retries_cnt++;
+ loop_cnt = 0;
+ udelay(10);
+ }
+ vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+ }
+ return SR_PASS;
+}
+
static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
{
u32 nvalue_reciprocal, v;
@@ -541,6 +586,8 @@ int sr_stop_vddautocomap(int srid)
sr_disable(sr);
sr_clk_disable(sr);
sr->is_autocomp_active = 0;
+ /* Reset the volatage for current OPP */
+ sr_reset_voltage(srid);
return SR_TRUE;
} else {
printk(KERN_WARNING "SR%d: VDD autocomp is not active\n",
@@ -609,6 +656,8 @@ void disable_smartreflex(int srid)
OMAP3430_GR_MOD,
OMAP3_PRM_VP2_CONFIG_OFFSET);
}
+ /* Reset the volatage for current OPP */
+ sr_reset_voltage(srid);
}
}
}--