===================================================================
@@ -218,7 +218,7 @@ int resource_set_opp_level(int res, u32
/* Send pre notification to CPUFreq */
cpufreq_notify_transition(&freqs_notify, CPUFREQ_PRECHANGE);
#endif
- t_opp = ID_VDD(PRCM_VDD1) |
+ t_opp = ID_VDD(VDD1_OPP) |
ID_OPP_NO(mpu_opps[target_level].opp_id);
if (resp->curr_level > target_level) {
/* Scale Frequency and then voltage */
@@ -245,7 +245,7 @@ int resource_set_opp_level(int res, u32
return 0;
l3_freq = get_freq(l3_opps + MAX_VDD2_OPP,
target_level);
- t_opp = ID_VDD(PRCM_VDD2) |
+ t_opp = ID_VDD(VDD2_OPP) |
ID_OPP_NO(l3_opps[target_level].opp_id);
if (resp->curr_level > target_level) {
/* Scale Frequency and then voltage */
@@ -266,7 +266,7 @@ int resource_set_opp_level(int res, u32
if (ret) {
#ifdef CONFIG_OMAP_SMARTREFLEX
/* Setting clock failed, revert voltage */
- t_opp = ID_VDD(PRCM_VDD2) |
+ t_opp = ID_VDD(VDD2_OPP) |
ID_OPP_NO(l3_opps[resp->curr_level].
opp_id);
sr_voltagescale_vcbypass(t_opp,
===================================================================
@@ -676,7 +676,7 @@ int sr_voltagescale_vcbypass(u32 target_
vdd = get_vdd(target_opp);
target_opp_no = get_opp_no(target_opp);
- if (vdd == PRCM_VDD1) {
+ if (vdd == VDD1_OPP) {
sr_status = sr_stop_vddautocomap(SR1);
prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
@@ -685,7 +685,7 @@ int sr_voltagescale_vcbypass(u32 target_
OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
reg_addr = R_VDD1_SR_CONTROL;
- } else if (vdd == PRCM_VDD2) {
+ } else if (vdd == VDD2_OPP) {
sr_status = sr_stop_vddautocomap(SR2);
prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
@@ -724,9 +724,9 @@ int sr_voltagescale_vcbypass(u32 target_
udelay(T2_SMPS_UPDATE_DELAY);
if (sr_status) {
- if (vdd == PRCM_VDD1)
+ if (vdd == VDD1_OPP)
sr_start_vddautocomap(SR1, target_opp_no);
- else if (vdd == PRCM_VDD2)
+ else if (vdd == VDD2_OPP)
sr_start_vddautocomap(SR2, target_opp_no);
}
===================================================================
@@ -171,9 +171,6 @@
/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE values */
#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
-/* VDDs*/
-#define PRCM_VDD1 1
-#define PRCM_VDD2 2
#define PRCM_MAX_SYSC_REGS 30
/*--