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[PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset

Message ID 5A47E75E594F054BAF48C5E4FC4B92AB03229868BA@dbde02.ent.ti.com (mailing list archive)
State Changes Requested, archived
Delegated to: Paul Walmsley
Headers show

Commit Message

Reddy, Teerth April 23, 2010, 11:14 a.m. UTC 
None
diff mbox

Patch

diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 9537f6f..e0a4e98 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -27,6 +27,7 @@ 
 #include <plat/prcm.h>
 #include <plat/irqs.h>
 #include <plat/control.h>
+#include <plat/sram.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
@@ -141,6 +142,8 @@  void omap_prcm_arch_reset(char mode, const char *cmd)
 		omap2xxx_clk_prepare_for_reboot();
 
 		prcm_offs = WKUP_MOD;
+		prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+						 OMAP2_RM_RSTCTRL);
 	} else if (cpu_is_omap34xx()) {
 		u32 l;
 
@@ -152,14 +155,15 @@  void omap_prcm_arch_reset(char mode, const char *cmd)
 		 * cf. OMAP34xx TRM, Initialization / Software Booting
 		 * Configuration. */
 		omap_writel(l, OMAP343X_SCRATCHPAD + 4);
+		/* Disable interrupts before reset */
+		local_irq_disable();
+		/* This function does not return */
+		omap3_warmreset();
 	} else if (cpu_is_omap44xx())
 		prcm_offs = OMAP4430_PRM_DEVICE_MOD;
 	else
 		WARN_ON(1);
 
-	if (cpu_is_omap24xx() | cpu_is_omap34xx())
-		prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
-						 OMAP2_RM_RSTCTRL);
 	if (cpu_is_omap44xx())
 		prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
 						 OMAP4_RM_RSTCTRL);
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index de99ba2..ab9b7db 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -33,6 +33,8 @@ 
 
 #include "sdrc.h"
 #include "cm.h"
+#include "prcm-common.h"
+#include "prm.h"
 
 	.text
 
@@ -68,6 +70,9 @@ 
 /* CM_CLKSEL1_PLL bit settings */
 #define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b
 
+/* PRM_RSTCTRL bit setting */
+#define EN_DPLL3_RESET                  0x4
+
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
  *
@@ -313,3 +318,48 @@  core_m2_mask_val:
 ENTRY(omap3_sram_configure_core_dpll_sz)
 	.word	. - omap3_sram_configure_core_dpll
 
+
+/**
+ * omap3_sram_warmreset -
+ *
+ * Enable SDRC self refresh on idle request, put SDRC in idle,
+ * wait until SDRC goes to idle
+ * Enable DPLL3 reset bit in OMAP2_RM_RSTCTRL
+ */
+
+ENTRY(omap3_sram_warmreset)
+sdram_in_selfrefresh1:
+	ldr	r11, omap3_sdrc_power1  @ read the SDRC_POWER register
+	ldr	r12, [r11]              @ read the contents of SDRC_POWER
+	orr	r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
+	str	r12, [r11]              @ write back to SDRC_POWER register
+	ldr	r12, [r11]              @ posted-write barrier for SDRC
+	ldr	r11, omap3_cm_iclken1_core1     @ read the CM_ICLKEN1_CORE reg
+	ldr	r12, [r11]
+	bic	r12, r12, #EN_SDRC_MASK         @ disable iclk bit for SDRC
+	str	r12, [r11]
+wait_sdrc_idle2:
+	ldr	r11, omap3_cm_idlest1_core1
+	ldr	r12, [r11]
+	and	r12, r12, #ST_SDRC_MASK         @ check for SDRC idle
+	cmp	r12, #ST_SDRC_MASK
+	bne	wait_sdrc_idle2
+osw_warm_reset:
+	ldr	r11, omap3_reset_cntrl
+	ldr	r12, [r11]
+	orr	r12, r12, #EN_DPLL3_RESET       @ Enable DPLL3 reset bit
+	str	r12, [r11]
+osw_loop:
+	b	osw_loop
+
+omap3_reset_cntrl:
+	.word OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL)
+omap3_sdrc_power1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+omap3_cm_idlest1_core1:
+	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
+omap3_cm_iclken1_core1:
+	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
+
+ENTRY(omap3_sram_warmreset_sz)
+	.word   . - omap3_sram_warmreset
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 16a1b45..3e67822 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -27,6 +27,9 @@  extern u32 omap3_configure_core_dpll(
 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+extern void omap3_warmreset(void);
+
 extern void omap3_sram_restore_context(void);
 
 /* Do not use these */
@@ -69,6 +72,10 @@  extern u32 omap3_sram_configure_core_dpll(
 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
+extern void omap3_sram_warmreset(void);
+
+extern unsigned long omap3_sram_warmreset_sz;
+
 #ifdef CONFIG_PM
 extern void omap_push_sram_idle(void);
 #else
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 51f4dfb..94b162b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -410,6 +410,16 @@  u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 			sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
+/* Function for SDRC config for warm reset */
+static void (*_omap3_sram_warmreset)(void);
+
+void omap3_warmreset()
+{
+	WARN_ON(!_omap3_sram_warmreset);
+
+	return _omap3_sram_warmreset();
+}
+
 #ifdef CONFIG_PM
 void omap3_sram_restore_context(void)
 {
@@ -418,6 +428,10 @@  void omap3_sram_restore_context(void)
 	_omap3_sram_configure_core_dpll =
 		omap_sram_push(omap3_sram_configure_core_dpll,
 			       omap3_sram_configure_core_dpll_sz);
+	_omap3_sram_warmreset =
+		omap_sram_push(omap3_sram_warmreset,
+			       omap3_sram_warmreset_sz);
+
 	omap_push_sram_idle();
 }
 #endif /* CONFIG_PM */
@@ -427,6 +441,11 @@  int __init omap34xx_sram_init(void)
 	_omap3_sram_configure_core_dpll =
 		omap_sram_push(omap3_sram_configure_core_dpll,
 			       omap3_sram_configure_core_dpll_sz);
+
+	_omap3_sram_warmreset =
+		omap_sram_push(omap3_sram_warmreset,
+			       omap3_sram_warmreset_sz);
+
 	omap_push_sram_idle();
 	return 0;
 }