From patchwork Mon Jan 27 15:37:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 3542781 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 32B3C9F391 for ; Mon, 27 Jan 2014 15:39:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4ADD02015B for ; Mon, 27 Jan 2014 15:39:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3FA5F2015A for ; Mon, 27 Jan 2014 15:39:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753539AbaA0Pi5 (ORCPT ); Mon, 27 Jan 2014 10:38:57 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:54445 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753138AbaA0Pi4 (ORCPT ); Mon, 27 Jan 2014 10:38:56 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s0RFcGGJ003360; Mon, 27 Jan 2014 09:38:16 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s0RFcGUC018104; Mon, 27 Jan 2014 09:38:16 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Mon, 27 Jan 2014 09:38:16 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s0RFcFOe031985; Mon, 27 Jan 2014 09:38:15 -0600 From: Jyri Sarha To: , , , , CC: , , Jyri Sarha , , Subject: [PATCH RFC v3 1/8] clk: add gpio controlled clock Date: Mon, 27 Jan 2014 17:37:50 +0200 Message-ID: <818f319d34b2abe6ecaffc6d18cd9ef3820ceb30.1390836773.git.jsarha@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The added clk-gpio is a basic clock that can be enabled and disabled trough a gpio output. The DT binding document for the clock is also added. For EPROBE_DEFER handling the registering of the clock has to be delayed until of_clk_get() call time. Signed-off-by: Jyri Sarha cc: mturquette@linaro.org cc: bcousson@baylibre.com --- .../devicetree/bindings/clock/gpio-clock.txt | 21 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-gpio.c | 210 ++++++++++++++++++++ include/linux/clk-provider.h | 25 +++ 4 files changed, 257 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gpio-clock.txt create mode 100644 drivers/clk/clk-gpio.c diff --git a/Documentation/devicetree/bindings/clock/gpio-clock.txt b/Documentation/devicetree/bindings/clock/gpio-clock.txt new file mode 100644 index 0000000..54fea39 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gpio-clock.txt @@ -0,0 +1,21 @@ +Binding for simple gpio controlled clock. + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "gpio-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- enable-gpios : GPIO reference for enabling and disabling the clock. + +Optional properties: +- clocks: Maximum of one parent clock is supported. + +Example: + clock { + compatible = "gpio-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 7a10bc9..9616e3a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o obj-$(CONFIG_COMMON_CLK) += clk-gate.o obj-$(CONFIG_COMMON_CLK) += clk-mux.o obj-$(CONFIG_COMMON_CLK) += clk-composite.o +obj-$(CONFIG_COMMON_CLK) += clk-gpio.o # SoCs specific obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c new file mode 100644 index 0000000..e04b0e1 --- /dev/null +++ b/drivers/clk/clk-gpio.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2013 Texas Instruments + * Author: Jyri Sarha + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Gpio controlled clock implementation + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: basic gpio controlled clock which can be enabled and disabled + * with gpio output + * Traits of this clock: + * prepare - clk_(un)prepare only ensures parent is (un)prepared + * enable - clk_enable and clk_disable are functional & control gpio + * rate - inherits rate from parent. No clk_set_rate support + * parent - fixed parent. No clk_set_parent support + */ + +#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) + +static int clk_gpio_enable(struct clk_hw *hw) +{ + struct clk_gpio *gpio = to_clk_gpio(hw); + int value = gpio->active_low ? 0 : 1; + + gpio_set_value(gpio->gpio, value); + + return 0; +} + +static void clk_gpio_disable(struct clk_hw *hw) +{ + struct clk_gpio *gpio = to_clk_gpio(hw); + int value = gpio->active_low ? 1 : 0; + + gpio_set_value(gpio->gpio, value); +} + +static int clk_gpio_is_enabled(struct clk_hw *hw) +{ + struct clk_gpio *gpio = to_clk_gpio(hw); + int value = gpio_get_value(gpio->gpio); + + return gpio->active_low ? !value : value; +} + +const struct clk_ops clk_gpio_ops = { + .enable = clk_gpio_enable, + .disable = clk_gpio_disable, + .is_enabled = clk_gpio_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_gpio_ops); + +/** + * clk_register_gpio - register a gpip clock with the clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_name: name of this clock's parent + * @flags: framework-specific flags for this clock + * @gpio: gpio to control this clock + * @active_low: gpio polarity + */ +struct clk *clk_register_gpio(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned int gpio, bool active_low) +{ + struct clk_gpio *clk_gpio; + struct clk *clk = ERR_PTR(-EINVAL); + struct clk_init_data init = { NULL }; + unsigned long gpio_flags; + int err; + + if (active_low) + gpio_flags = GPIOF_OUT_INIT_LOW; + else + gpio_flags = GPIOF_OUT_INIT_HIGH; + + err = gpio_request_one(gpio, gpio_flags, name); + + if (err) { + pr_err("%s: %s: Error requesting clock control gpio %u\n", + __func__, name, gpio); + clk = ERR_PTR(err); + goto clk_register_gpio_err; + } + + clk_gpio = kzalloc(sizeof(*clk_gpio), GFP_KERNEL); + + if (!clk_gpio) { + pr_err("%s: %s: could not allocate gpio clk\n", __func__, name); + clk = ERR_PTR(-ENOMEM); + goto clk_register_gpio_err; + } + + init.name = name; + init.ops = &clk_gpio_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + clk_gpio->gpio = gpio; + clk_gpio->active_low = active_low; + clk_gpio->hw.init = &init; + + clk = clk_register(dev, &clk_gpio->hw); + + if (!IS_ERR(clk)) + return clk; + + kfree(clk_gpio); + +clk_register_gpio_err: + gpio_free(gpio); + + return clk; +} +EXPORT_SYMBOL_GPL(clk_register_gpio); + +#ifdef CONFIG_OF +/** + * The clk_register_gpio has to be delayed, because the EPROBE_DEFER + * can not be handled properly at of_clk_init() call time. + */ + +struct clk_gpio_delayed_register_data { + struct device_node *node; + struct mutex lock; /* Protect delayed clk registering */ + struct clk *clk; +}; + +static +struct clk *of_clk_gpio_delayed_register_get(struct of_phandle_args *clkspec, + void *_data) +{ + struct clk_gpio_delayed_register_data *data = + (struct clk_gpio_delayed_register_data *)_data; + struct clk *clk; + const char *clk_name = data->node->name; + const char *parent_name; + enum of_gpio_flags gpio_flags; + int gpio; + bool active_low; + + mutex_lock(&data->lock); + + if (data->clk) { + mutex_unlock(&data->lock); + return data->clk; + } + + gpio = of_get_named_gpio_flags(data->node, "enable-gpios", 0, + &gpio_flags); + + if (gpio < 0) { + mutex_unlock(&data->lock); + if (gpio != -EPROBE_DEFER) + pr_err("%s: %s: Can't get 'enable-gpios' DT property\n", + __func__, clk_name); + return ERR_PTR(gpio); + } + + active_low = gpio_flags & OF_GPIO_ACTIVE_LOW; + + parent_name = of_clk_get_parent_name(data->node, 0); + + clk = clk_register_gpio(NULL, clk_name, parent_name, 0, + gpio, active_low); + if (IS_ERR(clk)) { + mutex_unlock(&data->lock); + return clk; + } + + data->clk = clk; + mutex_unlock(&data->lock); + + return clk; +} + +/** + * of_gpio_clk_setup() - Setup function for gpio controlled clock + */ +void __init of_gpio_clk_setup(struct device_node *node) +{ + struct clk_gpio_delayed_register_data *data; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) { + pr_err("%s: could not allocate gpio clk\n", __func__); + return; + } + + data->node = node; + mutex_init(&data->lock); + + of_clk_add_provider(node, of_clk_gpio_delayed_register_get, data); +} +EXPORT_SYMBOL_GPL(of_gpio_clk_setup); +CLK_OF_DECLARE(gpio_clk, "gpio-clock", of_gpio_clk_setup); +#endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7e59253..21082b2 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -407,6 +407,31 @@ struct clk *clk_register_composite(struct device *dev, const char *name, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); +/*** + * struct clk_gpio - gpio controlled clock + * + * @hw: handle between common and hardware-specific interfaces + * @gpio: gpio + * @active_low: gpio polarity + * + * Clock with a gpio control for enabling and disabling the parent clock. + * Implements .enable, .disable and .is_enabled + */ + +struct clk_gpio { + struct clk_hw hw; + unsigned int gpio; + bool active_low; +}; + +extern const struct clk_ops clk_gpio_ops; + +struct clk *clk_register_gpio(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned int gpio, bool active_low); + +void of_gpio_clk_setup(struct device_node *node); + /** * clk_register - allocate a new clock, register it and return an opaque cookie * @dev: device that is registering this clock