From patchwork Tue Jan 25 21:34:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Tardy X-Patchwork-Id: 507061 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p0PLYslQ029978 for ; Tue, 25 Jan 2011 21:34:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754115Ab1AYVee (ORCPT ); Tue, 25 Jan 2011 16:34:34 -0500 Received: from mga14.intel.com ([143.182.124.37]:61017 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754112Ab1AYVed convert rfc822-to-8bit (ORCPT ); Tue, 25 Jan 2011 16:34:33 -0500 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 25 Jan 2011 13:34:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.60,376,1291622400"; d="scan'208";a="379833520" Received: from irsmsx602.ger.corp.intel.com ([163.33.3.242]) by azsmga001.ch.intel.com with ESMTP; 25 Jan 2011 13:34:31 -0800 Received: from irsmsx501.ger.corp.intel.com ([163.33.7.70]) by irsmsx602.ger.corp.intel.com ([163.33.3.242]) with mapi; Tue, 25 Jan 2011 21:34:29 +0000 From: "Tardy, Pierre" To: Linus Walleij , Chris Ball CC: "linux-mmc@vger.kernel.org" , Ohad Ben-Cohen , linux-omap Mailing List Date: Tue, 25 Jan 2011 21:34:28 +0000 Subject: RE: [PATCH v1 1/3]mmc: implemented runtime pm for mmc host Thread-Topic: [PATCH v1 1/3]mmc: implemented runtime pm for mmc host Thread-Index: Acu8E6hGlbhBHLhkRqaNj27Bb322hAAwo6rg Message-ID: <8250E4885F9967469CAC3FB5CBA2CE69934EFA98B2@irsmsx501.ger.corp.intel.com> References: <20110114082310.GB27523@intel.com> <8250E4885F9967469CAC3FB5CBA2CE69934E7AA2FE@irsmsx501.ger.corp.intel.com> <5D8008F58939784290FAB48F54975198351D4FA654@shsmsx502.ccr.corp.intel.com> <8250E4885F9967469CAC3FB5CBA2CE69934E7AAB20@irsmsx501.ger.corp.intel.com> <5D8008F58939784290FAB48F5497519835247E72AD@shsmsx502.ccr.corp.intel.com> <8250E4885F9967469CAC3FB5CBA2CE69934E7AACCC@irsmsx501.ger.corp.intel.com> <20110120050803.GA5732@void.printf.net> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 25 Jan 2011 21:34:57 +0000 (UTC) --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -20,6 +20,7 @@ #include #include #include +#include #include @@ -1221,6 +1222,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct sdhci_host *host; unsigned long flags; + unsigned int lastclock; u8 ctrl; host = mmc_priv(mmc); @@ -1231,6 +1233,27 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) goto out; /* + * get/put runtime_pm usage counter at ios->clock transitions + * We need to do it before any other chip access, as sdhci could + * be power gated + */ + lastclock = host->iosclock; + host->iosclock = ios->clock; + if (lastclock == 0 && ios->clock != 0) { + spin_unlock_irqrestore(&host->lock, flags); + pm_runtime_get_sync(host->mmc->parent); + spin_lock_irqsave(&host->lock, flags); + } else if (lastclock != 0 && ios->clock == 0) { + spin_unlock_irqrestore(&host->lock, flags); + pm_runtime_mark_last_busy(host->mmc->parent); + pm_runtime_put_autosuspend(host->mmc->parent); + spin_lock_irqsave(&host->lock, flags); + } + /* no need to configure the rest.. */ + if (host->iosclock == 0) + goto out; + + /* * Reset the chip on each power off. * Should clear out any weird states. */ @@ -1303,6 +1326,8 @@ static int sdhci_get_ro(struct mmc_host *mmc) I'm wondering if this code could be generic to all drivers, and if clock gating could not be taking/releasing reference counter on the mmc_bus whenever there is a clock gating transition? We could condition that on some MMC_CAP_POWERGATE_WILL_CLKGATE capability flag. Regards, Pierre --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company)