From patchwork Fri Dec 21 15:32:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Korsgaard X-Patchwork-Id: 1903651 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 58C853FE37 for ; Fri, 21 Dec 2012 15:39:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751496Ab2LUPjK (ORCPT ); Fri, 21 Dec 2012 10:39:10 -0500 Received: from mail-wi0-f179.google.com ([209.85.212.179]:60118 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751432Ab2LUPjI (ORCPT ); Fri, 21 Dec 2012 10:39:08 -0500 X-Greylist: delayed 377 seconds by postgrey-1.27 at vger.kernel.org; Fri, 21 Dec 2012 10:39:08 EST Received: by mail-wi0-f179.google.com with SMTP id o1so2833695wic.12 for ; Fri, 21 Dec 2012 07:39:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:subject:date:message-id:user-agent :mime-version:content-type; bh=u8ZyVg9xYvpHbH1LbvZbcbmOAtkdpQlxIODopJr0h7g=; b=muDE5X6/1aCgy2miPG7nttSymZJix/1R35P8vP+rCVkMEXVa5d9pCSP/Jvyq/r/AHC 7zFglmbmQbxAFT28mK+6Ca0+q0Xy//8nuJUSs3bP1csKDvsk2yiW9jTiiez3zXEJ7x4h iGzio3W5055m8DXAUw5VlHemD+T/xoOTfK0m3x8kSlaUHkVMsttnDNkeYYpdmj1Se3qe 1szBpEOchG0yoDlta0PMv0RHhsB/oVLqSkpYAuxj7Q5+td2IPDLHNdA8Ux/pVCIW2O8j MJgB8CUoCzMC1CK7rxPJCnff4cuhlYZFXctkroNVzmGCe11Yw1iHvEyQqKTa5SSTgcmE ctBA== X-Received: by 10.180.93.40 with SMTP id cr8mr24291771wib.15.1356103970920; Fri, 21 Dec 2012 07:32:50 -0800 (PST) Received: from dell.be.48ers.dk ([91.183.168.164]) by mx.google.com with ESMTPS id hi2sm24020642wib.10.2012.12.21.07.32.49 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Dec 2012 07:32:50 -0800 (PST) Received: from peko by dell.be.48ers.dk with local (Exim 4.80) (envelope-from ) id 1Tm4ae-0000VK-BJ for linux-omap@vger.kernel.org; Fri, 21 Dec 2012 16:32:48 +0100 From: Peter Korsgaard To: linux-omap@vger.kernel.org Subject: reset handling in am335x hwmod data Date: Fri, 21 Dec 2012 16:32:48 +0100 Message-ID: <87ehij8lpb.fsf@dell.be.48ers.dk> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.4 (gnu/linux) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hi, On a custom am335x board I was surprised to see the kernel resetting gpio pins not mentioned anywhere in the dts. In this specific case the pin is connected to nCONFIG of a FPGA. The FPGA is commanded to start configuration from a SPI flash in the bootloader, so it can happen in parallel with kernel load/uncompress/startup, but as the kernel resets the gpio during initialization this doesn't work. Digging a bit into it, I see the hwmod of the gpio controller is configured to reset at startup, and it works correctly (E.G. the pin is left asserted) if I change it to HWMOD_INIT_NO_RESET: Now the question is why is this configured like this? I don't have any experience with omap hwmod, but on other (non-TI) boards I haven't experienced similar issues. Should E.G. the gpio controllers be changed to not reset or should it be configurable in the dts? --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -992,7 +992,7 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { .name = "gpio2", .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .mpu_irqs = am33xx_gpio1_irqs, .main_clk = "l4ls_gclk", .prcm = {