[v4,2/2] OMAP:IOMMU:flush L1 and L2 caches

Commit Message

Gupta, Ramesh July 5, 2012, 5:20 a.m. UTC

From 393c4effbbec74ff9b969d53ce4d36fde56b71df Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G <[e-mail]>
Date: Fri, 15 Jun 2012 16:46:46 +0530
Subject: [PATCH v4 2/2] OMAP:IOMMU:flush L1 and L2 caches

OMAP IOMMU need to make sure that data in the L1 and L2
caches is visible to the MMU hardware whenever the
pagetables are updated. The current code only takes
care of L1 cache using assembly code. Added code to
handle this using a new L1 cache maintenance function
and the outer cache function.

Signed-off-by: Ramesh Gupta G <[e-mail]>
---
 drivers/iommu/omap-iommu.c |   26 +++++++++-----------------
 1 files changed, 9 insertions(+), 17 deletions(-)

 	} else {
@@ -542,7 +534,7 @@ static int iopgd_alloc_section(struct omap_iommu
*obj, u32 da, u32 pa, u32 prot)
 	}

 	*iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
-	flush_iopgd_range(iopgd, iopgd);
+	flush_iopgd_range(iopgd, iopgd + 1);
 	return 0;
 }

@@ -559,7 +551,7 @@ static int iopgd_alloc_super(struct omap_iommu
*obj, u32 da, u32 pa, u32 prot)

 	for (i = 0; i < 16; i++)
 		*(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
-	flush_iopgd_range(iopgd, iopgd + 15);
+	flush_iopgd_range(iopgd, iopgd + 16);
 	return 0;
 }

@@ -700,7 +692,7 @@ static size_t iopgtable_clear_entry_core(struct
omap_iommu *obj, u32 da)
 		}
 		bytes *= nent;
 		memset(iopte, 0, nent * sizeof(*iopte));
-		flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
+		flush_iopte_range(iopte, iopte + nent * sizeof(*iopte));

 		/*
 		 * do table walk to check if this table is necessary or not
@@ -722,7 +714,7 @@ static size_t iopgtable_clear_entry_core(struct
omap_iommu *obj, u32 da)
 		bytes *= nent;
 	}
 	memset(iopgd, 0, nent * sizeof(*iopgd));
-	flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
+	flush_iopgd_range(iopgd, iopgd + nent * sizeof(*iopgd));
 out:
 	return bytes;
 }

Comments

Russell King - ARM Linux Sept. 8, 2012, 10:17 a.m. UTC | #1

On Thu, Jul 05, 2012 at 10:50:24AM +0530, Gupta, Ramesh wrote:
>  static void flush_iopgd_range(u32 *first, u32 *last)
>  {
> -	/* FIXME: L2 cache should be taken care of if it exists */
> -	do {
> -		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pgd"
> -		    : : "r" (first));
> -		first += L1_CACHE_BYTES / sizeof(*first);
> -	} while (first <= last);
> +	flush_iommu_mem(first, last);
> +	outer_flush_range(virt_to_phys(first), virt_to_phys(last));

I think this would be safer if these operated on an area rather than a
range - which means taking a start plus size.

	phys_addr_t phys = virt_to_phys(start);

	iommu_flush_area(start, size);
	outer_flush_range(phys, phys + size);

is safer than the above if virt_to_phys() is non-linear.

>  		*iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
> -		flush_iopgd_range(iopgd, iopgd);
> +		flush_iopgd_range(iopgd, iopgd + 1);

And operating on a start + size also makes this kind of stuff clearer.
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Gupta, Ramesh Sept. 10, 2012, 10:25 a.m. UTC | #2

Hi Russell,


On Sat, Sep 8, 2012 at 3:47 PM, Russell King - ARM Linux
<[e-mail]> wrote:
> On Thu, Jul 05, 2012 at 10:50:24AM +0530, Gupta, Ramesh wrote:
>>  static void flush_iopgd_range(u32 *first, u32 *last)
>>  {
>> -     /* FIXME: L2 cache should be taken care of if it exists */
>> -     do {
>> -             asm("mcr        p15, 0, %0, c7, c10, 1 @ flush_pgd"
>> -                 : : "r" (first));
>> -             first += L1_CACHE_BYTES / sizeof(*first);
>> -     } while (first <= last);
>> +     flush_iommu_mem(first, last);
>> +     outer_flush_range(virt_to_phys(first), virt_to_phys(last));
>
> I think this would be safer if these operated on an area rather than a
> range - which means taking a start plus size.
>
>         phys_addr_t phys = virt_to_phys(start);
>
>         iommu_flush_area(start, size);
>         outer_flush_range(phys, phys + size);
>
> is safer than the above if virt_to_phys() is non-linear.

Agree, I will use the area.

>
>>               *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
>> -             flush_iopgd_range(iopgd, iopgd);
>> +             flush_iopgd_range(iopgd, iopgd + 1);
>
> And operating on a start + size also makes this kind of stuff clearer.

Sure, I will cleanup this and send an updated patch series.


Thank you for the inputs.

Best regards
Ramesh Gupta G
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Patch

diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 6899dcd..f909019 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -469,22 +469,14 @@  EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
  */
 static void flush_iopgd_range(u32 *first, u32 *last)
 {
-	/* FIXME: L2 cache should be taken care of if it exists */
-	do {
-		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pgd"
-		    : : "r" (first));
-		first += L1_CACHE_BYTES / sizeof(*first);
-	} while (first <= last);
+	flush_iommu_mem(first, last);
+	outer_flush_range(virt_to_phys(first), virt_to_phys(last));
 }

 static void flush_iopte_range(u32 *first, u32 *last)
 {
-	/* FIXME: L2 cache should be taken care of if it exists */
-	do {
-		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pte"
-		    : : "r" (first));
-		first += L1_CACHE_BYTES / sizeof(*first);
-	} while (first <= last);
+	flush_iommu_mem(first, last);
+	outer_flush_range(virt_to_phys(first), virt_to_phys(last));
 }

 static void iopte_free(u32 *iopte)
@@ -513,7 +505,7 @@  static u32 *iopte_alloc(struct omap_iommu *obj,
u32 *iopgd, u32 da)
 			return ERR_PTR(-ENOMEM);

 		*iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
-		flush_iopgd_range(iopgd, iopgd);
+		flush_iopgd_range(iopgd, iopgd + 1);

 		dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);