From patchwork Thu Sep 13 07:12:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Ramesh" X-Patchwork-Id: 1450451 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 9EDAE4025E for ; Thu, 13 Sep 2012 07:12:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751747Ab2IMHMV (ORCPT ); Thu, 13 Sep 2012 03:12:21 -0400 Received: from na3sys009aog130.obsmtp.com ([74.125.149.143]:59494 "EHLO na3sys009aog130.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751306Ab2IMHMU (ORCPT ); Thu, 13 Sep 2012 03:12:20 -0400 Received: from mail-ie0-f174.google.com ([209.85.223.174]) (using TLSv1) by na3sys009aob130.postini.com ([74.125.148.12]) with SMTP ID DSNKUFGHUzi73Y5ze1LqF5G5eGcJXSWqvt8B@postini.com; Thu, 13 Sep 2012 00:12:20 PDT Received: by ieje11 with SMTP id e11so4378043iej.19 for ; Thu, 13 Sep 2012 00:12:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:x-gm-message-state; bh=OAxNhuGGLH+7rNGfQLXcQ2iTq0B4n5aLntiKC0iVxmA=; b=kmw1bf8rQLgOaHSYhYoSpfqeKAAmQK0W9qtDdj+kMr3k8iOKXjJfbZOOCYMA4ASTIk ASQaSkQ2F4z2ulCRGYQRy4ANPTYQcwyyQxwK8Lc+w7SuRDfhWxEvZQ6B1F+NRTANT/2o ZdryOCyDlnkoDdbgZW+cXEEXQz2HC0e/9xVC2DbbOQ/jL608qzrfJmRqtvz3QkC2qB7v qQ7VZWzsO3Cim8BrWZeQFJOX46zz0Q4220THelk3jUWMmXzLhq/RFEB44jVq/SwQrAd5 Sfh4YFJQGFZp7jbYlD7XEdh9gNDXSgB65TiVv14Tc2skHkTRt8A2RSQj5mPMsh5JyjMQ ZmGQ== MIME-Version: 1.0 Received: by 10.42.84.69 with SMTP id k5mr969561icl.5.1347520339622; Thu, 13 Sep 2012 00:12:19 -0700 (PDT) Received: by 10.50.194.228 with HTTP; Thu, 13 Sep 2012 00:12:19 -0700 (PDT) In-Reply-To: References: <20120912164121.GF28448@n2100.arm.linux.org.uk> Date: Thu, 13 Sep 2012 12:42:19 +0530 Message-ID: Subject: [PATCH v6 2/2] OMAP:IOMMU:flush L1 and L2 caches From: "Gupta, Ramesh" To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org Cc: Russell King - ARM Linux , tony@atomide.com X-Gm-Message-State: ALoCoQn5HAnimQK1bzIuTj/JybRZ9li+efxeUdOmxjW7Xf9oRGfRag0wNreYm5yPIRz6oXeMWrSk Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From a00cbfadc0053a3c21812593997a1b7338234a9f Mon Sep 17 00:00:00 2001 From: Ramesh Gupta G Date: Wed, 12 Sep 2012 19:05:29 +0530 Subject: [PATCH v6 2/2] OMAP:IOMMU:flush L1 and L2 caches OMAP IOMMU need to make sure that data in the L1 and L2 caches is visible to the MMU hardware whenever the page tables are updated. The current code only takes care of L1 cache using assembly. Added code to handle this using a new L1 cache maintenance function and the outer cache function. Thanks to the RMK's suggestions. Signed-off-by: Ramesh Gupta G --- drivers/iommu/omap-iommu.c | 40 ++++++++++++++++++---------------------- 1 files changed, 18 insertions(+), 22 deletions(-) } else { @@ -544,7 +540,7 @@ static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) } *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_area(iopgd, sizeof(*iopgd)); return 0; } @@ -561,7 +557,7 @@ static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; - flush_iopgd_range(iopgd, iopgd + 15); + flush_iopgd_area(iopgd, sizeof(*iopgd) * 16); return 0; } @@ -574,7 +570,7 @@ static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) return PTR_ERR(iopte); *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; - flush_iopte_range(iopte, iopte); + flush_iopte_area(iopte, sizeof(*iopte)); dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", __func__, da, pa, iopte, *iopte); @@ -599,7 +595,7 @@ static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; - flush_iopte_range(iopte, iopte + 15); + flush_iopte_area(iopte, sizeof(*iopte) * 16); return 0; } @@ -702,7 +698,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) } bytes *= nent; memset(iopte, 0, nent * sizeof(*iopte)); - flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); + flush_iopte_area(iopte, (nent) * sizeof(*iopte)); /* * do table walk to check if this table is necessary or not @@ -724,7 +720,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) bytes *= nent; } memset(iopgd, 0, nent * sizeof(*iopgd)); - flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); + flush_iopgd_area(iopgd, (nent) * sizeof(*iopgd)); out: return bytes; } @@ -768,7 +764,7 @@ static void iopgtable_clear_entry_all(struct omap_iommu *obj) iopte_free(iopte_offset(iopgd, 0)); *iopgd = 0; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_area(iopgd, sizeof(*iopgd)); } flush_iotlb_all(obj); diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index d0b1234..d399493 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -469,24 +469,20 @@ EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); /* * H/W pagetable operations */ -static void flush_iopgd_range(u32 *first, u32 *last) +static void flush_iopgd_area(u32 *first, size_t size) { - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); + phys_addr_t phys = virt_to_phys(first); + + iommu_flush_area(first, size); + outer_flush_range(phys, phys + size); } -static void flush_iopte_range(u32 *first, u32 *last) +static void flush_iopte_area(u32 *first, size_t size) { - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); + phys_addr_t phys = virt_to_phys(first); + + iommu_flush_area(first, size); + outer_flush_range(phys, phys + size); } static void iopte_free(u32 *iopte) @@ -515,7 +511,7 @@ static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) return ERR_PTR(-ENOMEM); *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_area(iopgd, sizeof(*iopgd)); dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);