From patchwork Wed Sep 12 15:19:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Ramesh" X-Patchwork-Id: 1444941 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 10974DF28C for ; Wed, 12 Sep 2012 15:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758856Ab2ILPTV (ORCPT ); Wed, 12 Sep 2012 11:19:21 -0400 Received: from na3sys009aog103.obsmtp.com ([74.125.149.71]:47677 "EHLO na3sys009aog103.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758197Ab2ILPTR (ORCPT ); Wed, 12 Sep 2012 11:19:17 -0400 Received: from mail-pz0-f70.google.com ([209.85.210.70]) (using TLSv1) by na3sys009aob103.postini.com ([74.125.148.12]) with SMTP ID DSNKUFCn9d8EkXhyu7M4cFtC+g18OJkQ+uyt@postini.com; Wed, 12 Sep 2012 08:19:17 PDT Received: by dadv40 with SMTP id v40so2771300dad.1 for ; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:date:message-id:subject:from:to:cc:content-type :x-gm-message-state; bh=GQOrrhwPNBc+iIfRoOfrqQzssWi7pxKojfujKV0acxA=; b=j4Qg9r5MHLj+3LnUs1kzKQCZb3Hfi3TewYnTNTUY1RUwqigfKQIrunrbj3Rm8oWl33 oqut7JtToJHJEmPREpQWXYp2hVB7/VSCM1pGO5jYgHED/1ePrx6Bu3EV2a8tPv1CheO9 cKMo4eUqX9fDzbyhlKzLcWDn0TovFcfCLnSQDmr7Ot8REPp8djC7syW8xB38+rVEXtd8 1kYJhcazZblG1rWxomMl2YZX8m2Yk3JyIRKHNAvTXTgAoPC/UqYObwrTPBrHdJKD0yaF oTXIWnzmzb4p7FeKEnvZYamuShnfJAg4oAyr7Vn3PI9EAsWnmJW5UUov+dsyVoD9M40X lHcA== Received: by 10.66.80.98 with SMTP id q2mr22023321pax.29.1347463156594; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.66.80.98 with SMTP id q2mr22023311pax.29.1347463156464; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) Received: by 10.66.73.10 with HTTP; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) Date: Wed, 12 Sep 2012 20:49:16 +0530 Message-ID: Subject: [PATCH v5 2/2] OMAP:IOMMU:flush L1 and L2 caches From: "Gupta, Ramesh" To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org Cc: Russell King - ARM Linux , tony@atomide.com X-Gm-Message-State: ALoCoQnnf/J8NDdKjC2t0YVJr9r5TKTOUiyjIKtmGcLrbp0fvkL4EiMhrkrwc94z4GZdfJbp45PCcz0k1KpNo2wb6TUG/UdBr/g3OjuI0ObakvcytY5ySvDyV4wtPzhej3fnr/Aquq4fSzlhuFgUzp2gBOKH/aTjCb6gevF5PH4NvPNJh9ZKCzE= Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From d78ddb5b0dffed3fd77e6e010735e869ea41b02f Mon Sep 17 00:00:00 2001 From: Ramesh Gupta G Date: Wed, 12 Sep 2012 19:05:29 +0530 Subject: [PATCH v5 2/2] OMAP:IOMMU:flush L1 and L2 caches OMAP IOMMU need to make sure that data in the L1 and L2 caches is visible to the MMU hardware whenever the pagetables are updated. The current code only takes care of L1 cache using assembly. Added code to handle this using a new L1 cache maintenance function and the outer cache function. Thanks to the RMK's suggestions. Signed-off-by: Ramesh Gupta G --- drivers/iommu/omap-iommu.c | 41 +++++++++++++++++++---------------------- 1 files changed, 19 insertions(+), 22 deletions(-) } else { @@ -544,7 +541,7 @@ static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) } *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_range(iopgd, sizeof(*iopgd)); return 0; } @@ -561,7 +558,7 @@ static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; - flush_iopgd_range(iopgd, iopgd + 15); + flush_iopgd_range(iopgd, sizeof(*iopgd) * 16); return 0; } @@ -574,7 +571,7 @@ static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) return PTR_ERR(iopte); *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; - flush_iopte_range(iopte, iopte); + flush_iopte_range(iopte, sizeof(*iopte)); dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", __func__, da, pa, iopte, *iopte); @@ -599,7 +596,7 @@ static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; - flush_iopte_range(iopte, iopte + 15); + flush_iopte_range(iopte, sizeof(*iopte) * 16); return 0; } @@ -702,7 +699,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) } bytes *= nent; memset(iopte, 0, nent * sizeof(*iopte)); - flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); + flush_iopte_range(iopte, iopte + (nent) * sizeof(*iopte)); /* * do table walk to check if this table is necessary or not @@ -724,7 +721,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) bytes *= nent; } memset(iopgd, 0, nent * sizeof(*iopgd)); - flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); + flush_iopgd_range(iopgd, iopgd + (nent) * sizeof(*iopgd)); out: return bytes; } @@ -768,7 +765,7 @@ static void iopgtable_clear_entry_all(struct omap_iommu *obj) iopte_free(iopte_offset(iopgd, 0)); *iopgd = 0; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_range(iopgd, sizeof(*iopgd)); } flush_iotlb_all(obj); diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index d0b1234..8f61ef9 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -469,24 +469,21 @@ EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); /* * H/W pagetable operations */ -static void flush_iopgd_range(u32 *first, u32 *last) +static void flush_iopgd_range(u32 *first, size_t size) { - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); + phys_addr_t phys = virt_to_phys(first); + + iommu_flush_area(first, size); + outer_flush_range(phys, phys + size); } -static void flush_iopte_range(u32 *first, u32 *last) +static void flush_iopte_range(u32 *first, size_t size) + { - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); + phys_addr_t phys = virt_to_phys(first); + + iommu_flush_area(first, size); + outer_flush_range(phys, phys + size); } static void iopte_free(u32 *iopte) @@ -515,7 +512,7 @@ static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) return ERR_PTR(-ENOMEM); *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_range(iopgd, sizeof(*iopgd)); dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);