From patchwork Fri Aug 17 08:47:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1338071 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 398DEDF266 for ; Fri, 17 Aug 2012 08:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755965Ab2HQIr6 (ORCPT ); Fri, 17 Aug 2012 04:47:58 -0400 Received: from na3sys009aog122.obsmtp.com ([74.125.149.147]:48624 "EHLO na3sys009aog122.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755440Ab2HQIrx (ORCPT ); Fri, 17 Aug 2012 04:47:53 -0400 Received: from mail-yw0-f47.google.com ([209.85.213.47]) (using TLSv1) by na3sys009aob122.postini.com ([74.125.148.12]) with SMTP ID DSNKUC4FOFSoAxyZI7ji9ab9vmd7vCYxRKjV@postini.com; Fri, 17 Aug 2012 01:47:52 PDT Received: by yhjj56 with SMTP id j56so4107995yhj.6 for ; Fri, 17 Aug 2012 01:47:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=MxWi7mVhiS+jk9Y8iACQ5lEEfhpGL10h7JE4w1nCL+Y=; b=e0Ffq5E7bewa2l6QWuSNXVR3UExXGhPT9weE7rqDH5tAxlAUjwgR3JGK6qOUNkQVLt hGyC0zcqhtfE0ssr4D1nBrHK2tpPVyuAKfXu0CiEDwZVSq7aRckqn4ONMGcKdYF2YmFG ZCCH7DkjfASfczOPuyQj4+Fe68jT/tAiET4larcAwmRzvtOdCLb8WZ7I9SBPGhPCkDaE 4RuixhW33FVZTcYRnNvfZFI/3OROQriWZAyqkeKaBGL6ovjfOkA/8spL0aUmruM8tOLg i2R8WH36iyZXmSYXzWsY5mQJKvGZlaAZ2X1aLqhaAMT4zL1NczWVe9sZ05of2r8FWAXA lCNg== Received: by 10.50.15.133 with SMTP id x5mr1028767igc.26.1345193271560; Fri, 17 Aug 2012 01:47:51 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.65.85 with HTTP; Fri, 17 Aug 2012 01:47:31 -0700 (PDT) In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA8E131@DBDE01.ent.ti.com> References: <1344856045-15134-1-git-send-email-santosh.shilimkar@ti.com> <1344856045-15134-2-git-send-email-santosh.shilimkar@ti.com> <50293AC8.7010403@ti.com> <79CD15C6BA57404B839C016229A409A83EA8E131@DBDE01.ent.ti.com> From: "Shilimkar, Santosh" Date: Fri, 17 Aug 2012 14:17:31 +0530 Message-ID: Subject: Re: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter. To: "Hiremath, Vaibhav" Cc: "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.orig" , "tony@atomide.com" X-Gm-Message-State: ALoCoQnEnOktIn+DRqBF/z0XYiXyPmt2RvjRP4dzAyaCRfDTbAM5HmObG9arLcOaaKAChXWbdMHQ Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On Tue, Aug 14, 2012 at 11:52 AM, Hiremath, Vaibhav wrote: > > On Tue, Aug 14, 2012 at 11:46:35, Shilimkar, Santosh wrote: > > On Mon, Aug 13, 2012 at 11:05 PM, Vaibhav Hiremath > > wrote: > > > [...] > > > Also, does it make sense to get rid of hardcoded values above? > > > > > Actually not. Because the values are fixed since the counter > > clock-rate is hardwired to be 6.144 MHz and hence all the > > other numbers becomes constant. All these numbers are > > coming from TRM and not from any formula. I don't wanted > > to go on mathematical equation path since all the values > > are well documented. > > > > Yes, I looked at the TRM and they are well documented there. > I would atleast suggest you to state that, these values are coming > directly > from TRM and possibly give reference to the TRM section here. > Added the TRM chapter information and iounmap() change. Updated patch at end of the email. Regards Santosh From aae85431b1a0e985bbc5611972642e96a1501368 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 13 Aug 2012 14:24:24 +0530 Subject: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter. The real time counter also called master counter, is a free-running counter. It produces the count used by the CPU local timer peripherals in the MPU cluster. The timer counts at a rate of 6.144 MHz. The ratio registers needs to be configured based on system clock only onetime. After initialisation, hardware takes care of adjusting the clock in different low power modes to keep counter rate constant. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/Kconfig | 4 ++ arch/arm/mach-omap2/timer.c | 90 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 93 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dd2db02..2120f90 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL config SOC_HAS_OMAP2_SDRC bool "OMAP2 SDRAM Controller support" +config SOC_HAS_REALTIME_COUNTER + bool "Real time free running counter" + config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_OMAP2PLUS @@ -69,6 +72,7 @@ config SOC_OMAP5 select CPU_V7 select ARM_GIC select HAVE_SMP + select SOC_HAS_REALTIME_COUNTER comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2ff6d41..fd5c048 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -69,6 +69,11 @@ #define OMAP3_SECURE_TIMER 1 #endif +#define REALTIME_COUNTER_BASE 0x48243200 +#define INCREMENTER_NUMERATOR_OFFSET 0x10 +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 + /* Clockevent code */ static struct omap_dm_timer clkev; @@ -339,6 +344,84 @@ static void __init omap2_clocksource_init(int gptimer_id, omap2_gptimer_clocksource_init(gptimer_id, fck_source); } +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER +/* + * The realtime counter also called master counter, is a free-running + * counter, which is related to real time. It produces the count used + * by the CPU local timer peripherals in the MPU cluster. The timer counts + * at a rate of 6.144 MHz. Because the device operates on different clocks + * in different power modes, the master counter shifts operation between + * clocks, adjusting the increment per clock in hardware accordingly to + * maintain a constant count rate. + */ +static void __init realtime_counter_init(void) +{ + void __iomem *base; + static struct clk *sys_clk; + unsigned long rate; + unsigned int reg, num, den; + + base = ioremap(REALTIME_COUNTER_BASE, SZ_32); + if (!base) { + pr_err("%s: ioremap failed\n", __func__); + return; + } + sys_clk = clk_get(NULL, "sys_clkin_ck"); + if (!sys_clk) { + pr_err("%s: failed to get system clock handle\n", __func__); + iounmap(base); + return; + } + + rate = clk_get_rate(sys_clk); + /* Numerator/denumerator values refer TRM Realtime Counter section */ + switch (rate) { + case 1200000: + num = 64; + den = 125; + break; + case 1300000: + num = 768; + den = 1625; + break; + case 19200000: + num = 8; + den = 25; + break; + case 2600000: + num = 384; + den = 1625; + break; + case 2700000: + num = 256; + den = 1125; + break; + case 38400000: + default: + /* Program it for 38.4 MHz */ + num = 4; + den = 25; + break; + } + + /* Program numerator and denumerator registers */ + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= num; + __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); + + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= den; + __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + + iounmap(base); +} +#else +static inline void __init realtime_counter_init(void) +{} +#endif + #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ clksrc_nr, clksrc_src) \ static void __init omap##name##_timer_init(void) \ @@ -396,7 +479,12 @@ OMAP_SYS_TIMER(4) #endif #ifdef CONFIG_SOC_OMAP5 -OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) +static void __init omap5_timer_init(void) +{ + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); + omap2_clocksource_init(2, OMAP4_MPU_SOURCE); + realtime_counter_init(); +} OMAP_SYS_TIMER(5) #endif