From patchwork Tue Aug 21 09:41:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1353431 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 107E5DFFEC for ; Tue, 21 Aug 2012 09:42:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755854Ab2HUJmP (ORCPT ); Tue, 21 Aug 2012 05:42:15 -0400 Received: from na3sys009aog129.obsmtp.com ([74.125.149.142]:51079 "EHLO na3sys009aog129.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755087Ab2HUJmN (ORCPT ); Tue, 21 Aug 2012 05:42:13 -0400 Received: from mail-iy0-f172.google.com ([209.85.210.172]) (using TLSv1) by na3sys009aob129.postini.com ([74.125.148.12]) with SMTP ID DSNKUDNX9JNYP873LWS143JSltycz2bYX6bK@postini.com; Tue, 21 Aug 2012 02:42:13 PDT Received: by iabz21 with SMTP id z21so3574413iab.3 for ; Tue, 21 Aug 2012 02:42:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=kedXE3CNNkdF1FXyKQI0EeC46F/XCV8H3D4aVM/3DAU=; b=XM4lZ4yTiVojCZcsdoB4MZWHZpqVVK/mLnLMJUPkSLMs8NhWGPuvn3yKTuqJYVLRzh S3bNbWPF98u7+VeNjsdkb9Va3CWLfSLdoe5x8bgbTY7o/21pM+QzDw3KKBuyONk669YL FvdKHfUuUbPqGRkEJe54Px2lT2gDPdx/5aS2uBeONp5XKxRoMrC8Bs3u8LZTxYHgE5zR 8zzL5l8Ap9Nrk1JyEJt7QwCiMgivta3NXmtS+Oju+g0s34veI+KOcm1NjsGnFTxZSILv UmXLgkQCENv67d/3WWq5BGxXWhLjbDf6c01A/j+8WK5x4dK30DMPg282t/Jrio23HKKk YbLg== Received: by 10.42.22.206 with SMTP id p14mr13237790icb.23.1345542132074; Tue, 21 Aug 2012 02:42:12 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.65.85 with HTTP; Tue, 21 Aug 2012 02:41:51 -0700 (PDT) In-Reply-To: References: <1344855623-14879-1-git-send-email-santosh.shilimkar@ti.com> <1344855623-14879-5-git-send-email-santosh.shilimkar@ti.com> <503240EF.4050805@ti.com> From: "Shilimkar, Santosh" Date: Tue, 21 Aug 2012 15:11:51 +0530 Message-ID: Subject: Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree To: Benoit Cousson Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.or, tony@atomide.com X-Gm-Message-State: ALoCoQkHYoU6E9BHgtF0nEtfPPjLRzeLJZrwvsE5kPlzS8Kqhi2HLiAYw/aaWc8JBs4cftkcVp5x Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh wrote: > On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson wrote: >> Hi Santosh, >> >> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote: >>> This provides PL310 Level 2 Cache Controller Device Tree >>> support for OMAP4 based devices. >>> >>> Cc: Benoit Cousson >>> Signed-off-by: Santosh Shilimkar >>> --- >>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++ >>> arch/arm/mach-omap2/omap4-common.c | 6 +++++- >>> 2 files changed, 12 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi >>> index 6717c71..cf1efb6 100644 >>> --- a/arch/arm/boot/dts/omap4.dtsi >>> +++ b/arch/arm/boot/dts/omap4.dtsi >>> @@ -36,6 +36,13 @@ >>> }; >>> }; >>> >> >>> + L2: l2-cache-controller { >> >> The reg offset is missing: l2-cache-controller@48242000 >> >>> + compatible = "arm,pl310-cache"; >>> + reg = <0x48242000 0x1000>; >>> + cache-unified; >>> + cache-level = <2>; >>> + }; >>> + >> >> In theory, the L2 cache should be referenced from the CPUs. >> > Agree. > I have added the reference for the L2 controller in CPUs. Other information like L1 cache size etc can be added in cpu DT node with another patch. Updated patch below. Have also updated git branch accordingly. Regards Santosh From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 4 Jul 2012 17:57:34 +0530 Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree This provides PL310 Level 2 Cache Controller Device Tree support for OMAP4 based devices. Cc: Benoit Cousson Signed-off-by: Santosh Shilimkar Acked-by: Felipe Balbi --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ arch/arm/mach-omap2/omap4-common.c | 6 +++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6717c71..0229dd2 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -30,12 +30,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; }; + L2: l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c29dee9..6f95992 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void) /* Enable PL310 L2 Cache controller */ omap_smc1(0x102, 0x1); - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); + if (of_have_populated_dt()) + l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); + else + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); /* * Override default outer_cache.disable with a OMAP4