From patchwork Tue Sep 11 09:29:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1436181 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 2F9AEDFAF3 for ; Tue, 11 Sep 2012 09:30:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756802Ab2IKJaB (ORCPT ); Tue, 11 Sep 2012 05:30:01 -0400 Received: from na3sys009aog110.obsmtp.com ([74.125.149.203]:55682 "EHLO na3sys009aog110.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756697Ab2IKJaA (ORCPT ); Tue, 11 Sep 2012 05:30:00 -0400 Received: from mail-gg0-f198.google.com ([209.85.161.198]) (using TLSv1) by na3sys009aob110.postini.com ([74.125.148.12]) with SMTP ID DSNKUE8Elwxk6JsnrMEg465mVqEo9CuKnEJY@postini.com; Tue, 11 Sep 2012 02:29:59 PDT Received: by ggnl1 with SMTP id l1so357139ggn.1 for ; Tue, 11 Sep 2012 02:29:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=JxFkH0OeI5o5K/SRSwaIcWFt19E5csEBoJtdCqgC5z8=; b=LyuTcY6NMhmHnVIxAQfu/hZnK4nhlFR6rewIY4uegC7COjnPl86APmR/wIiWUXJdoF f81nEkEHNqmqAPIMODBsSydDjfaziFXv9H164YiEUxUebwnEpDwBw1okeqnSf0o6fb9h DlnyfYv10u6P17nUX+/hprjOICBbsCoqrwq9c4t879Igx7eXhNX0jMYAO7U06KJH5DO9 Axa481KTAlYLKp5DrVxg7YHQK3BU6oNPK9zt9xMtqFzvNGB6tHUbdBpq0ZExUqUR+nTk 7nkBufnOti0SGQ9TkgRMSM/EXA31vShScQ5yKxLeMNIHVCj1qppPElivUzRl/ZTGpDBG QyfQ== Received: by 10.52.34.108 with SMTP id y12mr6358518vdi.131.1347355798647; Tue, 11 Sep 2012 02:29:58 -0700 (PDT) Received: by 10.52.34.108 with SMTP id y12mr6358510vdi.131.1347355798563; Tue, 11 Sep 2012 02:29:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.58.77.74 with HTTP; Tue, 11 Sep 2012 02:29:38 -0700 (PDT) In-Reply-To: References: <1344856045-15134-1-git-send-email-santosh.shilimkar@ti.com> <1344856045-15134-3-git-send-email-santosh.shilimkar@ti.com> <504DE165.4000208@ti.com> <504DE79B.3090302@ti.com> From: "Shilimkar, Santosh" Date: Tue, 11 Sep 2012 14:59:38 +0530 Message-ID: Subject: Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support To: Benoit Cousson Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.orig, tony@atomide.com X-Gm-Message-State: ALoCoQnGndVUKTDBpnOa2C+rim2nMyDlPZcgek/XpXrEkztcF4mAuQSp7gqs/dJPYcANPMTqrHy6Gy42sQAmWo7G9CGG5ZbiH9NJeuIiEOmjAr6LFHGhqTF5pjx6s77dS4tUgkByJUJrXI/yD1CyTWPJGhva/UcwaEm4ysjdEqMOOmskJloJeZ4= Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Benoit, On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh wrote: > On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson wrote: >> [...] >> >> Silly question: Don't we have one arch-timer per CPU? >> >> >> > It is per CPU just like A9 TWD >> >> Shouldn't we have two nodes then? >> > I need to check this but arch timer DT node should be same > as the twd DT node. May be one node with reference to > each CPU node should do but am not too sure about the DT > nodes and how all that work. > Here is an updated patch based on our discussion. Thanks for comments. Let me know if you are ok with this version. From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 13 Aug 2012 14:39:03 +0530 Subject: [PATCH] ARM: OMAP5: Enable arch timer support Enable Cortex A15 generic timer support for OMAP5 based SOCs. The CPU local timers run on the free running real time counter clock. Signed-off-by: Santosh Shilimkar Acked-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 12 ++++++++++++ arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/timer.c | 7 +++++++ 3 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e5270..7b986ed 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -33,9 +33,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; cpu@1 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; }; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2120f90..53fb77c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -73,6 +73,7 @@ config SOC_OMAP5 select ARM_GIC select HAVE_SMP select SOC_HAS_REALTIME_COUNTER + select ARM_ARCH_TIMER comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 8f5b88b..46982d0 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "common.h" #include #include @@ -481,9 +482,15 @@ OMAP_SYS_TIMER(4) #ifdef CONFIG_SOC_OMAP5 static void __init omap5_timer_init(void) { + int err; + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); omap2_clocksource_init(2, OMAP4_MPU_SOURCE); realtime_counter_init(); + + err = arch_timer_of_register(); + if (err) + pr_err("%s: arch_timer_register failed %d\n", __func__, err); } OMAP_SYS_TIMER(5) #endif