diff mbox

[2/2] ARM: dts: OMAP3+: add clock nodes for CPU

Message ID CAOCHtYjaCBn2oOk66ef9wiz_GJnVwHDyx446_mrkipPoENaeUQ@mail.gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Robert Nelson Jan. 29, 2014, 7:29 p.m. UTC
On Wed, Jan 29, 2014 at 12:19 PM, Nishanth Menon <nm@ti.com> wrote:
> OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.
>
> OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
> dpll_mpu clock.
>
> Latency used is the generic latency defined in omap-cpufreq
> driver.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>

Hi Nishanth,

After this patch, do you see any limitation to finally enabling 1Ghz
operation on the beagle-xm by default? Or are we still missing a
dependicy somewhere?

cpufreq stats: 300 MHz:98.64%, 600 MHz:0.04%, 800 MHz:0.09%, 1000
MHz:1.23%  (11)
full cpufreq output: http://paste.debian.net/79073/

+
        memory {
                device_type = "memory";
                reg = <0x80000000 0x20000000>; /* 512 MB */

Comments

Nishanth Menon Jan. 29, 2014, 11:32 p.m. UTC | #1
On 01/29/2014 01:29 PM, Robert Nelson wrote:
> On Wed, Jan 29, 2014 at 12:19 PM, Nishanth Menon <nm@ti.com> wrote:
>> OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.
>>
>> OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
>> dpll_mpu clock.
>>
>> Latency used is the generic latency defined in omap-cpufreq
>> driver.
>>
>> Signed-off-by: Nishanth Menon <nm@ti.com>
> 
> Hi Nishanth,
> 
> After this patch, do you see any limitation to finally enabling 1Ghz
> operation on the beagle-xm by default? Or are we still missing a
> dependicy somewhere?

yes, there is:
a) ABB dt series - i will repost this in a few mins
b) AVS conversion from non-dt mode to dt supported mode. (which by
itself depends on VC/VP conversion).
c) clk notifier based dvfs for cpufreq-cpu0 -> this allows us to
introduce the necessary plumbing for mpu voltage domain such that the
TWL4030 regulator, AVS and ABB are rightly sequenced.

What you have done in the patch below is to introduce ABB regulator -
but no one is actually using it -> this might actually work on certain
samples at 1GHz, but prolonged operation will either damage the device
or fail on other samples - I have tried numerous times Internally to
get approval for non ABB/AVS configuration for 1GHz - but I have a
clear feedback that it cannot be done with the constraints of
DM3730/OMAP3630.

Lets do this a series at a time and build up the necessary support -
we get clock nodes for dvfs (using i2c1) here with cpufreq-cpu0 with
this series. If folks can ack and queue this up, we can get in ABB dts
nodes in place - allowing us to work on the next set -> sequencing
using clock notifier. in parallel we could work on converting AVS back
to dt based solution.

yes, the road is long.
diff mbox

Patch

diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index bb5dad0..b0e5863 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -16,9 +16,36 @@ 
        cpus {
                cpu@0 {
                        cpu0-supply = <&vcc>;
+                       operating-points = <
+                               /* kHz    uV */
+                               300000   1012500
+                               600000   1200000
+                               800000   1325000
+                               1000000  1380000
+                       >;
                };
        };

+       abb: regulator-abb {
+               compatible = "ti,abb-v1";
+               regulator-name = "abb";
+               #address-cell = <0>;
+               #size-cells = <0>;
+               reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+               reg-names = "base-address", "int-address";
+               ti,tranxdone-status-mask = <0x4000000>;
+               clocks = <&dpll1_ck>;
+               ti,settling-time = <30>;
+               ti,clock-cycles = <8>;
+               ti,abb_info = <
+                       /* uV           ABB     efuse   rbb_m   fbb_m
 vset_m */
+                       1012500         0       0       0       0
 0 /* Bypass */
+                       1200000         3       0       0       0
 0 /* RBB mandatory */
+                       1320000         1       0       0       0
 0 /* FBB mandatory */
+                       1380000         1       0       0       0       0
+                       >;
+       };